Compare:

Old:explore-04ca53e65f-20261014-114124 at 04ca53e65fb234695323008abe2ef10c7cd13b1c
New:explore-bc8218b282-20261015-075519 at bc8218b282ea64c08087dfc5e1c5955349afc9ee

Mutants differ between runs unless the seeds and inputs are identical, so NEW categories can move between runs by chance.

Status:

StatusOldNew
identical1689316661(-232)
different55705311(-259)
gisel-better18312465(+634)
gisel-worse2058023200(+2620)
fallback1631821147(+4829)
crash696702(+6)

Only in new run (36):

KindCountCategory
fallback118legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s32
fallback83legalize: G_FSUB <4 x s32>
fallback75legalize: G_AND <2 x s64>
fallback44legalize: G_ADD <2 x s64>
fallback41translate: fdiv bfloat
fallback30legalize: G_XOR <4 x s32>
fallback15legalize: G_PHI <4 x s32>
fallback14legalize: G_SDIV <4 x s32>
fallback12legalize: G_SUB <4 x s32>
fallback11legalize: G_FMUL s128
fallback7legalize: G_INSERT_VECTOR_ELT <4 x s32>,s32
fallback5legalize: G_XOR <2 x s64>
fallback4legalize: G_INSERT_SUBVECTOR <vscale x 4 x s8>,<8 x s8>
fallback4legalize: G_LOAD <32 x s16>,p0
fallback4legalize: G_INSERT_VECTOR_ELT <4 x s16>,s16,s32
fallback4legalize: G_STORE p1,p0
crash4Assertion failed: (DstTy.getElementType() == SrcVecTy.getElementType() && "Extract subvector VTs must have the same element type!"), function buildInstr, file MachineIRBuilder.cpp
fallback3legalize: G_INSERT_VECTOR_ELT <4 x s32>,s32,s64
crash3error: <unknown>:0:0: ran out of registers during register allocation in function 'relax_jal_spill_64'
fallback2translate: extractelement <vscale x 2 x i64>
fallback2translate: icmp <vscale x 4 x i32>
fallback2translate: srem <vscale x 4 x i32>
fallback2legalize: G_INTRINSIC_W_SIDE_EFFECTS <2 x s32>,p0,<2 x s1>,s64,s32
fallback1legalize: G_MERGE_VALUES s128,s64
fallback1legalize: G_CTLZ_ZERO_POISON s32,s256
fallback1legalize: G_OR <2 x s16>
fallback1legalize: G_LOAD s64,p10,s32
fallback1legalize: G_LOAD s32,p10
fallback1legalize: G_EXTRACT_VECTOR_ELT s1,<4 x s1>,s64
fallback1legalize: G_CTLZ_ZERO_POISON s64,s256
fallback1legalize: G_AND <2 x s16>
fallback1legalize: G_LOAD <4 x s8>,p0
fallback1legalize: G_PHI <2 x s64>
fallback1translate: icmp <vscale x 8 x i1>
fallback1legalize: G_INTRINSIC_W_SIDE_EFFECTS <2 x s32>,p0,<2 x s1>,s32
fallback1legalize: G_XOR <4 x s8>

Gone in new run (28):

KindCountCategory
fallback33translate: fsub bfloat
fallback6legalize: G_FDIV <32 x s16>
fallback6legalize: G_FMUL <32 x s32>
fallback5legalize: G_CTLZ_ZERO_POISON s32,s96
fallback5legalize: G_EXTRACT_VECTOR_ELT s32,<2 x s32>
crash4LLVM ERROR: Found 1 machine code errors.
fallback3legalize: G_UDIV <2 x s64>
fallback3legalize: G_INSERT_VECTOR_ELT <32 x s16>,s16,s32
fallback3legalize: G_INSERT_VECTOR_ELT <32 x s16>,s16,s64
fallback2legalize: G_PHI <8 x s8>
fallback2legalize: G_FDIV <3 x s32>
fallback2legalize: G_UREM <4 x s32>
fallback2legalize: G_STORE p10,p0
fallback2select: G_SPLAT_VECTOR <vscale x 2 x s64>,s64
fallback1legalize: G_EXTRACT_VECTOR_ELT s64,<2 x s64>
fallback1legalize: G_SREM <2 x s64>
fallback1legalize: G_EXTRACT_VECTOR_ELT s32,<8 x s32>,s64
fallback1legalize: G_SEXTLOAD s32,p10,s16
fallback1legalize: G_CTLZ s32,s128
fallback1legalize: G_MUL <2 x s64>
fallback1legalize: G_INSERT_VECTOR_ELT <3 x s32>,s32,s64
fallback1legalize: G_AND <4 x s8>
fallback1legalize: G_SEXTLOAD s64,p10,s16
fallback1legalize: G_SREM <2 x s16>
fallback1legalize: G_SHUFFLE_VECTOR <2 x s64>
fallback1legalize: G_EXTRACT_VECTOR_ELT s64,<2 x s64>,s32
fallback1legalize: G_OR <4 x s8>
fallback1legalize: G_INSERT_VECTOR_ELT <3 x s32>,s32

Count changed (451):

KindOldNewCategory
fallback4902009(+1519)legalize: G_STORE <4 x s1>,p0
fallback2631570(+1307)legalize: G_STORE <2 x s1>,p0
fallback1490(+489)legalize: G_ADD <4 x s32>
fallback53853(-485)legalize: G_OR <2 x s64>
fallback634343(-291)translate: fcmp bfloat
fallback119358(+239)legalize: G_STORE <8 x s1>,p0
fallback17811(-167)legalize: G_SHL <2 x s64>
fallback18821(-167)legalize: G_LSHR <2 x s64>
fallback9801137(+157)unable to lower arguments
fallback2118(+116)legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s64
fallback87184(+97)legalize: G_LOAD <4 x s32>,p0
fallback74158(+84)legalize: G_CLMUL s16
fallback11547(-68)legalize: G_LSHR <4 x s32>
fallback775(+68)legalize: G_ASHR <4 x s32>
fallback55122(+67)legalize: G_LOAD <8 x s8>,p0
fallback55120(+65)legalize: G_ASHR <2 x s64>
fallback2373(+50)legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>,s64
fallback566(-50)legalize: G_AND <8 x s8>
fallback451(+47)legalize: G_MUL <8 x s8>
fallback147(+46)legalize: G_EXTRACT_VECTOR_ELT s8,<8 x s8>,s64
fallback1862(+44)legalize: G_FSIN s16
fallback1761(+44)legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>
fallback340299(-41)legalize: G_FCONSTANT s16
fallback1253(+41)legalize: G_AND <4 x s32>
fallback343(+40)legalize: G_EXTRACT_VECTOR_ELT s8,<8 x s8>,s32
fallback3775(+38)translate: call llvm.experimental.constrained.fptosi.i32.f16
fallback541(+36)legalize: G_ADD <8 x s8>
fallback2457(+33)legalize: G_FABS s16
fallback3062(+32)legalize: G_FMUL s16
fallback120150(+30)translate: call
fallback4415(-29)legalize: G_SUB <2 x s64>
fallback3362(+29)legalize: G_FPTRUNC s16,s64
fallback9466(-28)legalize: G_CLMUL s4
fallback1239(+27)legalize: G_FDIV s16
fallback92118(+26)legalize: G_FFLOOR s16
fallback6741(-26)legalize: G_FSUB s16
fallback100126(+26)legalize: G_FPTOUI_SAT s32,s16
fallback6085(+25)legalize: G_FCANONICALIZE s64
fallback833(+25)legalize: G_XOR <8 x s8>
fallback4824(-24)legalize: G_STRICT_FSQRT s16
fallback4064(+24)legalize: G_FFREXP s16,s32
fallback88112(+24)legalize: G_STRICT_FMA s16
fallback5532(-23)legalize: G_SDIV <8 x s8>
fallback2750(+23)legalize: G_OR <8 x s8>
fallback124(+23)legalize: G_UREM <8 x s8>
fallback6385(+22)legalize: G_CLMUL s64
fallback110132(+22)legalize: G_STRICT_FCMP s1,s32
fallback126148(+22)legalize: G_STRICT_FCMP s1,s16
fallback3614(-22)legalize: G_FPTOUI_SAT s8,s16
fallback5071(+21)translate: call llvm.experimental.constrained.fptoui.i32.f16
fallback120141(+21)legalize: G_IMPLICIT_DEF <4 x s8>
fallback8059(-21)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0
fallback7192(+21)legalize: G_SITOFP s16,s32
fallback4222(-20)legalize: G_UMULH s32
fallback170190(+20)legalize: G_IMPLICIT_DEF <2 x s16>
fallback286305(+19)legalize: G_INTRINSIC s32
fallback2810(-18)legalize: G_FLOG s16
fallback2810(-18)legalize: G_FTAN s16
fallback114132(+18)legalize: G_STRICT_FCMP s1,s64
fallback1028(+18)legalize: G_FCOSH s16
fallback2810(-18)legalize: G_FATAN s16
fallback2442(+18)translate: call llvm.experimental.constrained.fptosi.i32.f64
fallback2810(-18)legalize: G_FMODF s16
fallback1028(+18)legalize: G_FPOW s16
fallback2846(+18)legalize: G_FEXP s16
fallback2442(+18)legalize: G_FFREXP s64,s32
fallback1734(+17)translate: call llvm.experimental.constrained.fptrunc.f16.f64
fallback3451(+17)translate: call llvm.experimental.constrained.fptoui.i64.f16
fallback3417(-17)translate: call llvm.experimental.constrained.fpext.f128.f16
fallback421(+17)legalize: G_FADD <4 x s32>
fallback1734(+17)translate: call llvm.experimental.constrained.sitofp.f16.i64
fallback1734(+17)translate: call llvm.experimental.constrained.fpext.f64.f16
fallback6851(-17)translate: call llvm.experimental.constrained.sitofp.f16.i16
fallback1734(+17)translate: call llvm.experimental.constrained.fptosi.i64.f16
fallback3417(-17)translate: call llvm.experimental.constrained.fpext.f32.f16
fallback5134(-17)translate: call llvm.experimental.constrained.uitofp.f16.i16
fallback1734(+17)translate: call llvm.experimental.constrained.fptrunc.f16.f128
fallback3248(+16)translate: fptrunc float
fallback1632(+16)translate: call llvm.experimental.constrained.ceil.f16
fallback5672(+16)legalize: G_FMINIMUM s32
fallback1632(+16)translate: call llvm.experimental.constrained.llround.i64.f16
fallback108124(+16)legalize: G_INTRINSIC_ROUND s16
fallback2812(-16)translate: frem bfloat
fallback2642(+16)translate: call llvm.experimental.constrained.sitofp.f32.i32
fallback1632(+16)translate: call llvm.experimental.constrained.rint.f16
fallback3248(+16)legalize: G_STRICT_FLDEXP s16,s32
fallback1632(+16)translate: call llvm.experimental.constrained.nearbyint.f16
fallback3045(+15)translate: call llvm.experimental.constrained.fptoui.i32.f32
fallback116131(+15)unable to translate in big endian mode
fallback2641(+15)legalize: G_LOAD <2 x s32>,p0
fallback140125(-15)legalize: G_CLMUL s8
fallback2814(-14)legalize: G_FPEXT s128,s16
fallback5238(-14)translate: call llvm.experimental.constrained.uitofp.f64.i32
fallback2539(+14)legalize: G_ADD <4 x s16>
fallback3246(+14)legalize: G_FPTOUI_SAT s64
fallback9278(-14)legalize: G_FPTOUI_SAT s64,s16
fallback4256(+14)legalize: G_FMINIMUM s16
fallback620(+14)legalize: G_FMAXIMUMNUM s16
fallback1428(+14)legalize: G_SUB <8 x s8>
fallback1124(+13)legalize: G_SHL <8 x s8>
fallback8396(+13)translate: call llvm.experimental.constrained.uitofp.f16.i32
fallback3850(+12)legalize: G_LOAD <2 x s64>,p0
fallback3648(+12)legalize: G_VAARG s32,p0
fallback108120(+12)legalize: G_STRICT_FCMPS s1,s64
fallback820(+12)legalize: G_LSHR <8 x s8>
fallback1224(+12)translate: call llvm.experimental.constrained.sin.f32
fallback5668(+12)legalize: G_UITOFP s16,s32
fallback108120(+12)legalize: G_STRICT_FCMPS s1,s32
fallback6678(+12)legalize: G_STRICT_FMA s32
fallback3018(-12)legalize: G_FFREXP <4 x s32>
fallback6678(+12)legalize: G_STRICT_FMA s64
fallback2436(+12)legalize: G_FFREXP s32
crash5062(+12)Assertion failed: (MI->getNumOperands() > OpNo + 1 && "Expected additional operand"), function bool, file RISCVAsmPrinter.cpp
fallback3244(+12)legalize: G_FPTOUI_SAT s64,s32
fallback108120(+12)legalize: G_STRICT_FCMPS s1,s16
fallback1224(+12)translate: call llvm.experimental.constrained.sin.f64
fallback3344(+11)legalize: G_FCANONICALIZE <8 x s16>
fallback2233(+11)legalize: G_FCANONICALIZE <4 x s16>
crash499488(-11)Assertion failed: (BestRC && "Couldn't find the register class"), function getCommonMinimalPhysRegClass, file TargetRegisterInfo.cpp
fallback4433(-11)legalize: G_FCANONICALIZE <2 x s32>
fallback1020(+10)legalize: G_CLMUL s48
fallback1828(+10)legalize: G_CLMUL <2 x s64>
fallback5848(-10)legalize: G_CLMUL s128
fallback7868(-10)legalize: G_FNEG s16
fallback8494(+10)legalize: G_INTRINSIC_TRUNC s16
fallback2818(-10)legalize: G_FDIV <4 x s32>
fallback3848(+10)translate: call llvm.experimental.constrained.sitofp.f64.i32
fallback7787(+10)legalize: G_INTRINSIC s64
fallback3545(+10)legalize: G_CLMUL s32
fallback313(+10)legalize: G_SREM <8 x s8>
fallback2838(+10)translate: call llvm.experimental.constrained.fptoui.i32.f64
fallback4435(-9)legalize: G_INSERT_VECTOR_ELT <2 x s64>,s64
fallback189(-9)legalize: G_FCANONICALIZE s16
fallback10192(-9)translate: call llvm.experimental.constrained.sitofp.f16.i32
fallback2820(-8)legalize: G_FLDEXP s16,s32
crash2012(-8)Assertion failed: (DstTy.isVector() && SrcVecTy.isVector() && "Extract subvector VTs must be vectors!"), function buildInstr, file MachineIRBuilder.cpp
fallback1826(+8)legalize: G_LOAD <4 x s16>,p0
fallback3644(+8)legalize: G_FPTOSI_SAT s32
fallback2416(-8)translate: call llvm.experimental.constrained.lrint.i32.f16
fallback1911(-8)select: G_LOAD s32,p0,s16
fallback1624(+8)translate: call llvm.experimental.constrained.lround.i32.f16
fallback2129(+8)legalize: G_SREM <4 x s16>
fallback1624(+8)legalize: G_FMAXIMUM s64
fallback816(+8)legalize: G_STRICT_FMUL s16
fallback92100(+8)legalize: G_INTRINSIC_ROUNDEVEN s16
fallback3442(+8)legalize: G_ATOMIC_CMPXCHG s32,p0
fallback2416(-8)translate: call llvm.experimental.constrained.lrint.i64.f16
fallback91(-8)legalize: G_UDIV <2 x s32>
fallback5648(-8)legalize: G_FMAXIMUM s32
fallback7466(-8)legalize: G_UMULH s64
fallback2230(+8)translate: fptrunc double
fallback106114(+8)legalize: G_FPTOSI_SAT s32,s16
fallback1624(+8)translate: call llvm.experimental.constrained.lround.i64.f16
fallback513(+8)legalize: G_UREM <4 x s16>
fallback2821(-7)legalize: G_VAARG s64,p0
fallback5360(+7)legalize: G_INTRINSIC s32,<2 x s16>
fallback29(+7)legalize: G_MUL <4 x s32>
fallback1017(+7)legalize: G_ATOMICRMW_MIN s64,p0
fallback1219(+7)legalize: G_ATOMICRMW_UMIN s64,p0
fallback512(+7)legalize: G_LSHR <4 x s16>
fallback1017(+7)legalize: G_SREM <4 x s32>
crash7683(+7)Assertion failed: (VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 && "unexpected custom value"), function int, file RISCVCallLowering.cpp
fallback613(+7)legalize: G_EXTRACT_VECTOR_ELT s16,<2 x s16>,s64
fallback612(+6)translate: call llvm.experimental.constrained.trunc.f32
fallback126(-6)translate: call llvm.experimental.constrained.fptosi.i128.f16
fallback126(-6)translate: call llvm.experimental.constrained.atan2.f64
fallback126(-6)translate: call llvm.experimental.constrained.fptosi.i64.f32
fallback612(+6)legalize: G_STRICT_FMUL s32
fallback612(+6)translate: call llvm.experimental.constrained.powi.f64
fallback6672(+6)legalize: G_INTRINSIC p0
fallback126(-6)translate: call llvm.experimental.constrained.tanh.f32
fallback126(-6)translate: call llvm.experimental.constrained.fptosi.i128.f64
fallback126(-6)translate: call llvm.experimental.constrained.log2.f64
fallback612(+6)translate: call llvm.experimental.constrained.uitofp.f32.i16
fallback126(-6)legalize: G_STRICT_FADD s32
fallback612(+6)translate: call llvm.experimental.constrained.sitofp.f64.i16
fallback1824(+6)legalize: G_ATOMICRMW_XCHG s32,p0
fallback612(+6)translate: call llvm.experimental.constrained.sitofp.f32.i8
fallback1218(+6)translate: call llvm.experimental.constrained.minnum.f64
fallback1218(+6)legalize: G_STRICT_FSQRT s32
fallback4236(-6)legalize: G_FPTOSI_SAT s64
fallback1218(+6)translate: call llvm.experimental.constrained.uitofp.f64.i64
fallback126(-6)translate: call llvm.experimental.constrained.log2.f32
fallback612(+6)translate: call llvm.experimental.constrained.nearbyint.f64
fallback126(-6)translate: call llvm.experimental.constrained.fptrunc.f32.f64
fallback126(-6)translate: call llvm.experimental.constrained.tanh.f64
fallback612(+6)translate: call llvm.experimental.constrained.exp.f32
fallback1218(+6)translate: call llvm.experimental.constrained.minnum.f32
fallback104(-6)legalize: G_UMULH s16
fallback3024(-6)translate: sitofp i32
fallback2418(-6)legalize: G_LOAD <2 x s16>,p0
fallback612(+6)translate: call llvm.experimental.constrained.tan.f32
fallback612(+6)translate: call llvm.experimental.constrained.trunc.f64
fallback612(+6)translate: call llvm.experimental.constrained.fptoui.i128.f32
fallback1218(+6)legalize: G_RESET_FPMODE
fallback410(+6)legalize: G_FSINCOS s64
fallback126(-6)translate: call llvm.experimental.constrained.atan2.f32
fallback137(-6)legalize: G_MUL <4 x s16>
fallback1812(-6)translate: call llvm.experimental.constrained.fptoui.i64.f32
fallback410(+6)legalize: G_EXTRACT_VECTOR_ELT s16,<2 x s16>,s32
fallback410(+6)legalize: G_FPTOUI_SAT s8,s32
fallback2228(+6)translate: fpext bfloat
fallback104(-6)legalize: G_FPTOSI_SAT s16,s64
fallback410(+6)legalize: G_FPTOSI_SAT s8,s64
fallback1218(+6)legalize: G_STRICT_FSQRT s64
fallback2127(+6)legalize: G_FFREXP s128,s32
fallback612(+6)translate: call llvm.experimental.constrained.fptoui.i128.f64
fallback126(-6)legalize: G_GET_FPENV s64
fallback612(+6)translate: call llvm.experimental.constrained.floor.f64
fallback612(+6)translate: call llvm.experimental.constrained.uitofp.f64.i8
fallback126(-6)translate: call llvm.experimental.constrained.rint.f64
fallback1218(+6)translate: sitofp i16
fallback1824(+6)translate: uitofp i32
fallback2834(+6)legalize: G_SET_ROUNDING s32
fallback612(+6)translate: call llvm.experimental.constrained.exp.f64
fallback612(+6)translate: call llvm.experimental.constrained.tan.f64
fallback1610(-6)legalize: G_SITOFP s128,s64
fallback612(+6)translate: call llvm.experimental.constrained.powi.f32
fallback410(+6)legalize: G_VECREDUCE_ADD s16,<16 x s16>
fallback1218(+6)legalize: G_STORE <3 x s11>,p0
fallback1218(+6)translate: call llvm.experimental.constrained.uitofp.f32.i8
fallback612(+6)translate: call llvm.experimental.constrained.nearbyint.f32
fallback104(-6)silent fallback (no remark emitted)
fallback4236(-6)legalize: G_FPTOSI_SAT s64,s32
fallback5662(+6)legalize: G_FPTOUI_SAT s32,s64
fallback126(-6)translate: call llvm.experimental.constrained.rint.f32
fallback612(+6)translate: call llvm.experimental.constrained.fptoui.i128.f16
fallback1218(+6)legalize: G_RESET_FPENV
fallback612(+6)legalize: G_STRICT_FMUL s64
fallback612(+6)translate: call llvm.experimental.constrained.floor.f32
fallback612(+6)translate: call llvm.experimental.constrained.sitofp.f64.i64
fallback126(-6)translate: call llvm.experimental.constrained.fptosi.i128.f32
fallback612(+6)legalize: G_STORE <3 x s1>,p0
fallback126(-6)legalize: G_GET_FPENV s32
fallback5247(-5)legalize: G_INVOKE_REGION_START
fallback1914(-5)legalize: G_BITCAST s64,<8 x s8>
fallback27(+5)legalize: G_FPTOSI_SAT s128,s16
fallback2823(-5)legalize: G_FCANONICALIZE s32
fallback116(-5)legalize: G_STORE <32 x s1>,p0
fallback230235(+5)select: G_GLOBAL_VALUE p0
fallback3530(-5)translate: fadd bfloat
fallback38(+5)legalize: G_FPTOSI_SAT s128,s64
fallback1318(+5)legalize: G_BITCAST s64,<4 x s16>
fallback1510(-5)legalize: G_CLMUL s96
fallback7378(+5)legalize: G_BLOCK_ADDR p0
fallback27(+5)legalize: G_FPTOSI_SAT s128,s32
fallback4650(+4)translate: call llvm.experimental.constrained.uitofp.f32.i32
fallback3640(+4)legalize: G_FPTOSI_SAT s32,s64
fallback26(+4)legalize: G_STORE <16 x s1>,p0
fallback1713(-4)legalize: G_STRICT_FADD s64
fallback812(+4)legalize: G_SREM <4 x s64>
fallback84(-4)legalize: G_FPTOUI_SAT s16,s32
fallback84(-4)legalize: G_EXTRACT_VECTOR_ELT s32,<2 x s32>,s64
fallback221225(+4)legalize: G_FADD s16
fallback1814(-4)legalize: G_ZEXTLOAD s128,p0,s64
fallback1612(-4)legalize: G_SUB <4 x s64>
fallback62(-4)legalize: G_SHUFFLE_VECTOR <4 x s8>
fallback4036(-4)legalize: G_FMINIMUM s64
fallback3943(+4)legalize: G_INSERT_SUBVECTOR <vscale x 2 x s32>,<4 x s32>
fallback26(+4)legalize: G_INSERT_VECTOR_ELT <4 x s16>,s16,s64
fallback610(+4)legalize: G_INSERT_SUBVECTOR <vscale x 1 x s32>,<2 x s32>
fallback1410(-4)translate: call llvm.masked.load.nxv2i64.p0
fallback51(-4)legalize: G_OR <4 x s32>
fallback48(+4)legalize: G_ADDRSPACE_CAST p10,p0
fallback84(-4)legalize: G_FSINCOS s32
fallback48(+4)legalize: G_ATOMICRMW_ADD s16,p0
fallback1814(-4)legalize: G_GET_ROUNDING s32
fallback1418(+4)legalize: G_FPTOSI_SAT s8,s16
fallback51(-4)legalize: G_FSUB s128
fallback26(+4)legalize: G_VECREDUCE_OR s32,<4 x s32>
fallback4642(-4)legalize: G_ATOMICRMW_XOR s32,p0
fallback48(+4)legalize: G_LOAD <16 x s32>,p0
fallback1014(+4)select: G_JUMP_TABLE p0
fallback812(+4)translate: call llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64
fallback84(-4)legalize: G_SITOFP s16,s128
fallback128(-4)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0,s32
fallback610(+4)translate: lshr <vscale x 2 x i32>
fallback106(-4)select: G_INTRINSIC_W_SIDE_EFFECTS <vscale x 4 x s32>,s64
fallback26(+4)legalize: G_VECREDUCE_FMIN s32,<4 x s32>
fallback4448(+4)legalize: G_LOAD <16 x s8>,p0
crash117(-4)Assertion failed: (Bits != 0 && "Cannot print this instruction."), function printInstruction, file RISCVGenAsmWriter.inc
fallback26(+4)legalize: G_SMULH s8
fallback48(+4)legalize: G_ATOMICRMW_ADD s8,p0
fallback6662(-4)legalize: G_ATOMICRMW_NAND s32,p0
fallback26(+4)legalize: G_FEXP10 <2 x s32>
fallback36(+3)translate: call llvm.experimental.constrained.lrint.i32.f64
fallback1411(-3)legalize: G_ATOMICRMW_UMIN s64,p0,s32
fallback25(+3)legalize: G_LSHR <4 x s64>
fallback36(+3)translate: call llvm.experimental.constrained.lrint.i32.f32
fallback811(+3)translate: call llvm.is.fpclass.nxv4f32
fallback47(+3)legalize: G_UMULH s8
fallback47(+3)legalize: G_UMULH s128
fallback1411(-3)legalize: G_ATOMICRMW_UMIN s32,p0
crash47(+3)Assertion failed: ((MeaningfulBitWidth.isScalable() || OrigValueBitWidth >= MeaningfulBitWidth) && "Meaningful bits not covered by the mapping"), function verify, file RegisterBankInfo.cpp
fallback58(+3)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0,s64
fallback912(+3)translate: call llvm.experimental.constrained.sitofp.f32.i128
fallback69(+3)legalize: G_FPTOUI_SAT s128,s64
fallback25(+3)legalize: G_CTLZ_ZERO_POISON s32,s200
fallback25(+3)legalize: G_CTLZ_ZERO_POISON s64,s200
fallback4441(-3)legalize: G_INTRINSIC s64,<2 x s32>

Generated 2026-10-15 08:05 UTC.