Compare:

Old:main-04ca53e65f-20261014-113325 at 04ca53e65fb234695323008abe2ef10c7cd13b1c
New:explore-04ca53e65f-20261014-114124 at 04ca53e65fb234695323008abe2ef10c7cd13b1c

Mutants differ between runs unless the seeds and inputs are identical, so NEW categories can move between runs by chance.

Status:

StatusOldNew
identical1736716893(-474)
different57645570(-194)
gisel-better24521831(-621)
gisel-worse2182120580(-1241)
fallback2002916318(-3711)
crash728696(-32)

Only in new run (31):

KindCountCategory
fallback44legalize: G_INSERT_VECTOR_ELT <2 x s64>,s64,s32
fallback44legalize: G_INSERT_VECTOR_ELT <2 x s64>,s64
fallback33translate: fsub bfloat
fallback12legalize: G_AND <4 x s32>
fallback6legalize: G_FMUL <32 x s32>
fallback6legalize: G_FDIV <32 x s16>
fallback5legalize: G_CTLZ_ZERO_POISON s32,s96
fallback5legalize: G_EXTRACT_VECTOR_ELT s32,<2 x s32>
fallback4legalize: G_INSERT_SUBVECTOR <vscale x 2 x s16>,<4 x s16>
crash4LLVM ERROR: Found 1 machine code errors.
fallback3legalize: G_UDIV <2 x s64>
fallback3legalize: G_INSERT_VECTOR_ELT <32 x s16>,s16,s32
fallback3legalize: G_INSERT_VECTOR_ELT <32 x s16>,s16,s64
fallback2legalize: G_MUL <4 x s32>
fallback2legalize: G_PHI <8 x s8>
fallback2legalize: G_ICMP <2 x s1>,<2 x s64>
fallback2legalize: G_FDIV <3 x s32>
fallback2legalize: G_STORE p10,p0
fallback2select: G_SPLAT_VECTOR <vscale x 2 x s64>,s64
fallback1legalize: G_EXTRACT_VECTOR_ELT s64,<2 x s64>
fallback1legalize: G_EXTRACT_VECTOR_ELT s32,<8 x s32>,s64
fallback1legalize: G_SEXTLOAD s32,p10,s16
fallback1legalize: G_CTLZ s32,s128
fallback1legalize: G_INSERT_VECTOR_ELT <3 x s32>,s32,s64
fallback1legalize: G_AND <4 x s8>
fallback1legalize: G_SEXTLOAD s64,p10,s16
fallback1legalize: G_SREM <2 x s16>
fallback1legalize: G_SHUFFLE_VECTOR <2 x s64>
fallback1legalize: G_EXTRACT_VECTOR_ELT s64,<2 x s64>,s32
fallback1legalize: G_OR <4 x s8>
fallback1legalize: G_INSERT_VECTOR_ELT <3 x s32>,s32

Gone in new run (43):

KindCountCategory
fallback42legalize: G_AND <2 x s64>
fallback41legalize: G_FSUB <4 x s32>
fallback38legalize: G_SDIV <4 x s32>
fallback14legalize: G_SUB <4 x s32>
fallback13legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s32
fallback12legalize: G_XOR <4 x s32>
fallback12legalize: G_XOR <2 x s64>
fallback11translate: fdiv bfloat
crash8Assertion failed: (DstTy.getElementType() == SrcVecTy.getElementType() && "Extract subvector VTs must have the same element type!"), function buildInstr, file MachineIRBuilder.cpp
fallback5legalize: G_UDIV <4 x s32>
fallback4translate: icmp <vscale x 1 x i1>
fallback4legalize: G_INSERT_VECTOR_ELT <4 x s16>,s16,s32
fallback4legalize: G_STORE p1,p0
fallback3legalize: G_INSERT_VECTOR_ELT <4 x s32>,s32,s64
fallback3legalize: G_SDIV <2 x s64>
fallback3legalize: G_INSERT_VECTOR_ELT <4 x s32>,s32
fallback2translate: lshr <vscale x 4 x i32>
fallback2legalize: G_XOR <2 x s16>
fallback2translate: urem <vscale x 1 x i64>
fallback2legalize: G_OR <16 x s16>
fallback2legalize: G_SREM <4 x s8>
fallback2legalize: G_FMUL s128
fallback2legalize: G_UDIV <16 x s32>
fallback2translate: icmp <vscale x 2 x i32>
fallback2translate: extractelement <vscale x 16 x i8>
fallback2translate: sdiv <vscale x 2 x i32>
fallback1legalize: G_MERGE_VALUES s128,s64
fallback1legalize: G_INTRINSIC_W_SIDE_EFFECTS <4 x s8>,p0,<4 x s1>,s64,s8
fallback1select: G_STORE s64,p0,s32
fallback1legalize: G_FREM s128
fallback1legalize: G_CTLZ_ZERO_POISON s32,s256
fallback1legalize: G_INSERT_VECTOR_ELT <4 x s8>,s8,s64
fallback1legalize: G_FMUL <2 x s32>
fallback1legalize: G_LOAD s32,p10
fallback1legalize: G_FDIV s128
fallback1legalize: G_CTLZ_ZERO_POISON s64,s256
fallback1legalize: G_SEXTLOAD s64,p10,s32
fallback1legalize: G_EXTRACT_VECTOR_ELT s32,<16 x s32>,s64
fallback1legalize: G_FSUB <32 x s16>
fallback1legalize: G_EXTRACT s64,s96
fallback1legalize: G_FSUB <32 x s32>
fallback1legalize: G_EXTRACT_VECTOR_ELT s32,<16 x s32>
fallback1translate: fcmp <32 x bfloat>

Count changed (448):

KindOldNewCategory
fallback1520263(-1257)legalize: G_STORE <2 x s1>,p0
fallback1237634(-603)translate: fcmp bfloat
fallback2538(+536)legalize: G_OR <2 x s64>
fallback812490(-322)legalize: G_STORE <4 x s1>,p0
fallback395119(-276)legalize: G_STORE <8 x s1>,p0
fallback31055(-255)legalize: G_LOAD <8 x s8>,p0
fallback517340(-177)legalize: G_FCONSTANT s16
fallback2178(+176)legalize: G_SHL <2 x s64>
fallback26188(+162)legalize: G_LSHR <2 x s64>
fallback1658(-157)legalize: G_XOR <8 x s8>
fallback18674(-112)legalize: G_CLMUL s16
fallback1087980(-107)unable to lower arguments
fallback1052(-103)legalize: G_UREM <4 x s32>
fallback957(-88)legalize: G_ASHR <8 x s8>
fallback31115(+84)legalize: G_LSHR <4 x s32>
fallback16787(-80)legalize: G_LOAD <4 x s32>,p0
fallback742(-72)translate: fmul bfloat
fallback684(-64)legalize: G_FADD <4 x s32>
fallback9128(-63)legalize: G_FDIV <4 x s32>
fallback455(+51)legalize: G_SDIV <8 x s8>
fallback6416(-48)translate: call llvm.experimental.constrained.ceil.f16
fallback10456(-48)legalize: G_FMINIMUM s32
fallback6619(-47)legalize: G_FMUL <4 x s32>
fallback4894(+46)legalize: G_CLMUL s4
fallback177221(+44)legalize: G_FADD s16
fallback7937(-42)translate: call llvm.experimental.constrained.fptosi.i32.f16
fallback3474(+40)legalize: G_UMULH s64
fallback4610(-36)legalize: G_FSINH s16
fallback4510(-35)legalize: G_SREM <4 x s32>
fallback2155(+34)legalize: G_ASHR <2 x s64>
fallback1648(+32)translate: call llvm.experimental.constrained.round.f16
fallback9058(-32)legalize: G_FMA s16
fallback7442(-32)legalize: G_FMINIMUM s16
fallback408(-32)legalize: G_STRICT_FMUL s16
fallback4816(-32)translate: call llvm.experimental.constrained.nearbyint.f16
fallback4818(-30)legalize: G_FSIN s16
fallback2858(+30)legalize: G_LSHR <2 x s128>
fallback5627(-29)legalize: G_OR <8 x s8>
fallback8960(-29)legalize: G_FCANONICALIZE s64
fallback10983(-26)translate: call llvm.experimental.constrained.uitofp.f16.i32
fallback5480(+26)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0
fallback337(-26)legalize: G_ASHR <4 x s32>
fallback6238(-24)legalize: G_LOAD <2 x s64>,p0
fallback339(-24)legalize: G_CTLZ_ZERO_POISON s32,s128
fallback11692(-24)legalize: G_FFLOOR s16
fallback3256(+24)legalize: G_FMAXIMUM s32
fallback4724(-23)legalize: G_FABS s16
fallback528(+23)translate: frem bfloat
fallback241(-23)legalize: G_SHL <4 x s32>
fallback3658(+22)legalize: G_CLMUL s128
fallback1436(+22)legalize: G_FPTOUI_SAT s8,s16
fallback2244(+22)legalize: G_FCANONICALIZE <2 x s32>
fallback231(-22)legalize: G_EXTRACT_VECTOR_ELT s8,<8 x s8>,s64
fallback4221(-21)legalize: G_SREM <4 x s16>
fallback9978(-21)legalize: G_FNEG s16
fallback265(-21)legalize: G_ADD <8 x s8>
fallback3514(-21)legalize: G_SUB <8 x s8>
fallback2242(+20)legalize: G_UMULH s32
fallback233(-20)legalize: G_EXTRACT_VECTOR_ELT s8,<8 x s8>,s32
fallback4930(-19)translate: call llvm.experimental.constrained.fptoui.i32.f32
fallback305286(-19)legalize: G_INTRINSIC s32
fallback1028(+18)legalize: G_FLDEXP s16,s32
fallback1028(+18)legalize: G_FLOG s16
fallback246(-18)legalize: G_STRICT_FMUL s32
fallback132114(-18)legalize: G_STRICT_FCMP s1,s64
fallback2810(-18)legalize: G_FEXP2 s16
fallback128110(-18)legalize: G_STRICT_FCMP s1,s32
fallback1028(+18)legalize: G_FATAN s16
fallback4224(-18)translate: call llvm.experimental.constrained.fptosi.i32.f64
fallback1028(+18)legalize: G_FMODF s16
fallback2810(-18)legalize: G_FPOW s16
fallback1028(+18)legalize: G_FEXP s16
fallback246(-18)legalize: G_STRICT_FMUL s64
fallback3417(-17)translate: call llvm.experimental.constrained.uitofp.f16.i64
fallback1734(+17)translate: call llvm.experimental.constrained.fptoui.i64.f16
fallback1734(+17)translate: call llvm.experimental.constrained.fpext.f128.f16
fallback3417(-17)translate: call llvm.experimental.constrained.sitofp.f16.i64
fallback258(-17)legalize: G_LSHR <8 x s8>
fallback2912(-17)legalize: G_FDIV s16
fallback4225(-17)legalize: G_ADD <4 x s16>
fallback181(-17)legalize: G_UREM <8 x s8>
fallback3417(-17)translate: call llvm.experimental.constrained.fpext.f64.f16
fallback3417(-17)translate: call llvm.experimental.constrained.fptosi.i64.f16
fallback1734(+17)translate: call llvm.experimental.constrained.fptoui.i16.f16
fallback5033(-17)legalize: G_FPTRUNC s16,s64
fallback181(-17)legalize: G_UDIV <8 x s8>
fallback3451(+17)translate: call llvm.experimental.constrained.uitofp.f16.i16
fallback3248(+16)legalize: G_STRICT_FSQRT s16
fallback8266(-16)legalize: G_INTRINSIC p0
fallback182(-16)legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s64
fallback116100(-16)legalize: G_FPTOUI_SAT s32,s16
fallback3216(-16)translate: call llvm.experimental.constrained.rint.f16
fallback171(-16)legalize: G_ADD <4 x s32>
fallback10488(-16)legalize: G_STRICT_FMA s16
fallback122106(-16)legalize: G_FPTOSI_SAT s32,s16
fallback1632(+16)translate: call llvm.experimental.constrained.floor.f16
fallback3216(-16)translate: call llvm.experimental.constrained.trunc.f16
fallback2642(+16)legalize: G_FMAXIMUM s16
fallback5671(+15)legalize: G_SITOFP s16,s32
fallback3116(-15)legalize: G_BITCAST s64,<2 x s32>
fallback1428(+14)legalize: G_FPEXT s128,s16
fallback130116(-14)unable to translate in big endian mode
fallback2814(-14)legalize: G_FPTRUNC s16,s128
fallback4632(-14)legalize: G_FPTOUI_SAT s64
fallback2410(-14)legalize: G_FMINNUM s16
fallback140126(-14)legalize: G_STRICT_FCMP s1,s16
fallback244230(-14)select: G_GLOBAL_VALUE p0
crash6450(-14)Assertion failed: (MI->getNumOperands() > OpNo + 1 && "Expected additional operand"), function bool, file RISCVAsmPrinter.cpp
fallback126140(+14)legalize: G_CLMUL s8
fallback3952(+13)legalize: G_INVOKE_REGION_START
fallback2411(-13)legalize: G_SHL <8 x s8>
fallback3144(+13)legalize: G_SUB <2 x s64>
fallback133120(-13)translate: call
fallback2235(+13)translate: fadd bfloat
fallback4835(-13)legalize: G_CLMUL s32
fallback164(-12)legalize: G_MUL <8 x s8>
fallback4836(-12)legalize: G_FPTOSI_SAT s32,s64
fallback1224(+12)translate: call llvm.experimental.constrained.maxnum.f64
fallback7563(-12)legalize: G_CLMUL s64
fallback4836(-12)legalize: G_FPTOSI_SAT s32
fallback186(-12)translate: call llvm.experimental.constrained.uitofp.f32.i16
fallback2412(-12)translate: call llvm.experimental.constrained.minnum.f64
fallback6250(-12)translate: call llvm.experimental.constrained.fptoui.i32.f16
fallback2412(-12)translate: call llvm.experimental.constrained.sin.f32
fallback186(-12)translate: call llvm.experimental.constrained.nearbyint.f64
fallback2412(-12)translate: call llvm.experimental.constrained.minnum.f32
fallback1830(+12)translate: sitofp i32
fallback416(+12)legalize: G_SUB <4 x s64>
fallback1224(+12)translate: call llvm.experimental.constrained.maxnum.f32
fallback3927(-12)legalize: G_SUB <4 x s16>
fallback1830(+12)legalize: G_FFREXP <4 x s32>
fallback3624(-12)legalize: G_FFREXP s32
fallback3321(-12)legalize: G_FFREXP s128,s32
fallback186(-12)translate: call llvm.experimental.constrained.uitofp.f64.i8
fallback4432(-12)legalize: G_FPTOUI_SAT s64,s32
fallback186(-12)translate: call llvm.experimental.constrained.nearbyint.f32
fallback2412(-12)legalize: G_RESET_FPENV
fallback2412(-12)translate: call llvm.experimental.constrained.sin.f64
fallback3624(-12)legalize: G_FFREXP s64,s32
fallback4433(-11)legalize: G_FCANONICALIZE <8 x s16>
fallback3322(-11)legalize: G_FCANONICALIZE <2 x s64>
fallback3322(-11)legalize: G_FCANONICALIZE <2 x s16>
fallback4030(-10)legalize: G_FMUL s16
fallback144(-10)legalize: G_UMULH s8
fallback6656(-10)legalize: G_UITOFP s16,s32
crash509499(-10)Assertion failed: (BestRC && "Couldn't find the register class"), function getCommonMinimalPhysRegClass, file TargetRegisterInfo.cpp
fallback7666(-10)legalize: G_ATOMICRMW_NAND s32,p0
fallback918(+9)legalize: G_FCANONICALIZE s16
fallback6556(-9)legalize: G_AND <8 x s8>
fallback189(-9)translate: call llvm.experimental.constrained.sitofp.f32.i128
fallback189(-9)translate: call llvm.experimental.constrained.sitofp.f16.i128
fallback189(-9)translate: call llvm.experimental.constrained.sitofp.f64.i128
fallback2432(+8)translate: fptrunc float
fallback816(+8)legalize: G_STRICT_FADD s16
fallback2618(-8)legalize: G_CLMUL <2 x s64>
fallback1810(-8)legalize: G_ATOMICRMW_MIN s64,p0
fallback1624(+8)translate: call llvm.experimental.constrained.lrint.i32.f16
fallback816(+8)translate: call llvm.experimental.constrained.lround.i32.f16
fallback1624(+8)legalize: G_LOAD <2 x s16>,p0
fallback513(+8)legalize: G_MUL <4 x s16>
fallback816(+8)legalize: G_STRICT_FSUB s16
fallback7078(+8)legalize: G_FPTOSI_SAT s64,s16
fallback1624(+8)translate: call llvm.experimental.constrained.lrint.i64.f16
fallback412(+8)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0,s32
fallback19(+8)legalize: G_UDIV <2 x s32>
fallback210(+8)select: G_INTRINSIC_W_SIDE_EFFECTS <vscale x 4 x s32>,s64
fallback2820(-8)select: G_PREFETCH p0
fallback4856(+8)legalize: G_FPTOUI_SAT s32,s64
fallback108100(-8)legalize: G_FCEIL s16
fallback816(+8)translate: call llvm.experimental.constrained.lround.i64.f16
fallback3628(-8)translate: call llvm.experimental.constrained.fptoui.i32.f64
fallback3528(-7)legalize: G_VAARG s64,p0
fallback1017(+7)legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>
fallback126(-6)translate: call llvm.experimental.constrained.exp2.f32
fallback126(-6)legalize: G_STRICT_FDIV s32
fallback2418(-6)legalize: G_LOAD <4 x s16>,p0
fallback612(+6)translate: call llvm.experimental.constrained.atan2.f64
fallback612(+6)translate: call llvm.experimental.constrained.llround.i64.f64
fallback4236(-6)legalize: G_VAARG s32,p0
fallback612(+6)translate: call llvm.experimental.constrained.log2.f64
fallback126(-6)legalize: G_STRICT_FDIV s64
fallback612(+6)legalize: G_STRICT_FADD s32
fallback612(+6)translate: call llvm.experimental.constrained.fptosi.i64.f64
fallback126(-6)translate: call llvm.experimental.constrained.sitofp.f64.i16
fallback126(-6)translate: call llvm.experimental.constrained.sitofp.f32.i8
fallback1812(-6)legalize: G_STRICT_FSQRT s32
fallback28(+6)legalize: G_EXTRACT_VECTOR_ELT s32,<2 x s32>,s64
fallback1319(+6)select: G_LOAD s32,p0,s16
fallback612(+6)translate: call llvm.experimental.constrained.log2.f32
fallback612(+6)translate: call llvm.experimental.constrained.fptrunc.f32.f64
fallback126(-6)translate: call llvm.experimental.constrained.acos.f64
fallback126(-6)translate: call llvm.experimental.constrained.acos.f32
fallback126(-6)translate: call llvm.experimental.constrained.uitofp.f64.i16
fallback126(-6)translate: call llvm.experimental.constrained.exp.f32
fallback612(+6)translate: call llvm.experimental.constrained.llround.i64.f32
fallback410(+6)legalize: G_UMULH s16
fallback1218(+6)legalize: G_ZEXTLOAD s128,p0,s64
fallback6066(+6)legalize: G_STRICT_FMA s32
fallback126(-6)translate: call llvm.experimental.constrained.tan.f32
fallback3238(+6)translate: call llvm.experimental.constrained.sitofp.f64.i32
fallback612(+6)translate: call llvm.experimental.constrained.asin.f32
fallback1812(-6)legalize: G_RESET_FPMODE
fallback612(+6)translate: call llvm.experimental.constrained.fpext.f64.f32
fallback612(+6)translate: call llvm.experimental.constrained.atan2.f32
fallback8692(+6)legalize: G_FPTOUI_SAT s64,s16
fallback2026(+6)legalize: G_LOAD <2 x s32>,p0
fallback1218(+6)translate: call llvm.experimental.constrained.fptoui.i64.f32
fallback612(+6)legalize: G_STRICT_FSUB s32
fallback3226(-6)translate: call llvm.experimental.constrained.sitofp.f32.i32
fallback612(+6)translate: call llvm.experimental.constrained.roundeven.f32
fallback1218(+6)legalize: G_GET_ROUNDING s32
fallback159(-6)legalize: G_SMULH s16
fallback6066(+6)legalize: G_STRICT_FMA s64
fallback93(-6)legalize: G_FPTOSI_SAT s128,s64
crash8276(-6)Assertion failed: (VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 && "unexpected custom value"), function int, file RISCVCallLowering.cpp
fallback126(-6)translate: call llvm.experimental.constrained.exp2.f64
fallback1812(-6)legalize: G_STRICT_FSQRT s64
fallback612(+6)legalize: G_GET_FPENV s64
fallback1812(-6)legalize: G_STORE <3 x s33>,p0
fallback1812(-6)translate: sitofp i16
fallback612(+6)translate: call llvm.experimental.constrained.roundeven.f64
fallback126(-6)translate: call llvm.experimental.constrained.exp.f64
fallback126(-6)translate: call llvm.experimental.constrained.tan.f64
fallback1812(-6)legalize: G_STORE <3 x s11>,p0
fallback82(-6)legalize: G_VECREDUCE_FMIN s32,<4 x s32>
fallback612(+6)translate: call llvm.experimental.constrained.asin.f64
fallback1812(-6)translate: uitofp i16
fallback612(+6)translate: call llvm.experimental.constrained.sitofp.f32.i64
fallback612(+6)legalize: G_STRICT_FSUB s64
fallback126(-6)translate: call llvm.experimental.constrained.sitofp.f64.i64
fallback612(+6)legalize: G_GET_FPENV s32
fallback116(-5)legalize: G_FPTOUI_SAT s128,s64
fallback4439(-5)legalize: G_INSERT_SUBVECTOR <vscale x 2 x s32>,<4 x s32>
fallback72(-5)legalize: G_INSERT_VECTOR_ELT <4 x s16>,s16,s64
fallback6267(+5)legalize: G_FSUB s16
fallback1015(+5)legalize: G_CLMUL s96
crash611(+5)Assertion failed: (Bits != 0 && "Cannot print this instruction."), function printInstruction, file RISCVGenAsmWriter.inc
fallback116(-5)legalize: G_UREM <2 x s64>
fallback1923(+4)legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>,s64
fallback9793(-4)legalize: G_FPTRUNC s16,s32
crash1620(+4)Assertion failed: (DstTy.isVector() && SrcVecTy.isVector() && "Extract subvector VTs must be vectors!"), function buildInstr, file MachineIRBuilder.cpp
fallback4852(+4)translate: call llvm.experimental.constrained.uitofp.f64.i32
fallback84(-4)legalize: G_FSINCOS s128
crash128(-4)Assertion failed: (getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag"), function lowerInlineAsm, file InlineAsmLowering.cpp
fallback48(+4)legalize: G_SREM <4 x s64>
fallback84(-4)legalize: G_FPTOUI_SAT s128,s32
fallback95(-4)legalize: G_FPTOUI_SAT s128,s16
fallback8884(-4)legalize: G_INTRINSIC_W_SIDE_EFFECTS s32,p0
fallback84(-4)legalize: G_UMULH s128
fallback3842(+4)legalize: G_FPTOSI_SAT s64
fallback62(-4)legalize: G_FPTOSI_SAT s128,s16
fallback95(-4)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0,s64
fallback2016(-4)legalize: G_FMAXIMUM s64
fallback104108(+4)legalize: G_INTRINSIC_ROUND s16
fallback4044(+4)legalize: G_LOAD <8 x s16>,p0
fallback3228(-4)legalize: G_FCANONICALIZE s32
fallback84(-4)legalize: G_ADDRSPACE_CAST p10,p0
fallback174170(-4)legalize: G_IMPLICIT_DEF <2 x s16>
fallback2622(-4)translate: fpext bfloat
fallback106(-4)legalize: G_FCMP s32,s128
fallback15(+4)legalize: G_FSUB s128
fallback51(-4)legalize: G_MUL <2 x s64>
fallback2529(+4)legalize: G_INTRINSIC_W_SIDE_EFFECTS
fallback2016(-4)legalize: G_SITOFP s128,s64
fallback1822(+4)translate: fptrunc double
fallback62(-4)legalize: G_FPTOSI_SAT s128,s32
fallback4044(+4)legalize: G_LOAD <16 x s8>,p0
fallback1014(+4)legalize: G_INSERT_SUBVECTOR <vscale x 8 x s8>,<16 x s8>
fallback3842(+4)legalize: G_FPTOSI_SAT s64,s32
fallback84(-4)legalize: G_ATOMICRMW_ADD s8,p0
fallback62(-4)legalize: G_FEXP10 <2 x s32>
fallback7976(-3)legalize: G_INTRINSIC_W_SIDE_EFFECTS s64,p0,s32
fallback36(+3)legalize: G_SET_FPENV s64
fallback912(+3)translate: call llvm.experimental.constrained.fptosi.i128.f16
fallback52(-3)legalize: G_STORE <16 x s1>,p0
fallback912(+3)translate: call llvm.experimental.constrained.fptosi.i128.f64
fallback36(+3)legalize: G_SET_FPENV s32
fallback74(-3)legalize: G_LSHR <2 x s32>
fallback5249(-3)legalize: G_FPTOUI_SAT s32
fallback36(+3)legalize: G_SHUFFLE_VECTOR <4 x s8>
fallback96(-3)translate: call llvm.experimental.constrained.fptoui.i128.f32
fallback811(+3)legalize: G_STORE <32 x s1>,p0
fallback14(+3)legalize: G_ADD <8 x s16>
fallback41(-3)legalize: G_INSERT_SUBVECTOR <vscale x 16 x s32>,<32 x s32>
fallback96(-3)legalize: G_SET_FPMODE s64
fallback96(-3)translate: call llvm.experimental.constrained.fptoui.i128.f64
fallback96(-3)legalize: G_SET_FPMODE s32
fallback58(+3)legalize: G_SITOFP s16,s128
fallback7073(+3)legalize: G_BLOCK_ADDR p0
fallback1714(-3)legalize: G_ZEXTLOAD s256,p0,s128
fallback96(-3)translate: call llvm.experimental.constrained.fptoui.i128.f16
fallback912(+3)translate: call llvm.experimental.constrained.fptosi.i128.f32
fallback42(-2)legalize: G_UMULH <2 x s128>
fallback4846(-2)translate: call llvm.experimental.constrained.uitofp.f32.i32
fallback79(+2)legalize: G_INTRINSIC s32,<4 x s8>
fallback1614(-2)legalize: G_ATOMIC_CMPXCHG s64,p0
fallback42(-2)legalize: G_FPTOSI s128,s16
fallback42(-2)legalize: G_EXTRACT s64,s168
fallback1315(+2)legalize: G_ATOMICRMW_MAX s64,p0,s32
fallback42(-2)legalize: G_SMULH <2 x s128>

Generated 2026-10-15 08:05 UTC.