Compare:

Old:main-bc8218b282-20261015-074651 at bc8218b282ea64c08087dfc5e1c5955349afc9ee
New:explore-bc8218b282-20261015-075519 at bc8218b282ea64c08087dfc5e1c5955349afc9ee

Mutants differ between runs unless the seeds and inputs are identical, so NEW categories can move between runs by chance.

Status:

StatusOldNew
identical1735916661(-698)
different57635311(-452)
gisel-better24502465(+15)
gisel-worse2183223200(+1368)
fallback2005821147(+1089)
crash734702(-32)

Only in new run (24):

KindCountCategory
fallback53legalize: G_AND <4 x s32>
fallback46legalize: G_INSERT_VECTOR_ELT <2 x s64>,s64,s32
fallback44legalize: G_ADD <2 x s64>
fallback35legalize: G_INSERT_VECTOR_ELT <2 x s64>,s64
fallback15legalize: G_PHI <4 x s32>
fallback9legalize: G_MUL <4 x s32>
fallback4legalize: G_INSERT_SUBVECTOR <vscale x 4 x s8>,<8 x s8>
fallback4legalize: G_INSERT_SUBVECTOR <vscale x 2 x s16>,<4 x s16>
fallback4legalize: G_ICMP <2 x s1>,<2 x s64>
fallback4legalize: G_LOAD <32 x s16>,p0
crash3error: <unknown>:0:0: ran out of registers during register allocation in function 'relax_jal_spill_64'
fallback2translate: srem <vscale x 4 x i32>
fallback2translate: extractelement <vscale x 2 x i64>
fallback2translate: icmp <vscale x 4 x i32>
fallback2legalize: G_INTRINSIC_W_SIDE_EFFECTS <2 x s32>,p0,<2 x s1>,s64,s32
fallback1legalize: G_LOAD <4 x s8>,p0
fallback1legalize: G_OR <2 x s16>
fallback1legalize: G_LOAD s64,p10,s32
fallback1legalize: G_PHI <2 x s64>
fallback1translate: icmp <vscale x 8 x i1>
fallback1legalize: G_EXTRACT_VECTOR_ELT s1,<4 x s1>,s64
fallback1legalize: G_INTRINSIC_W_SIDE_EFFECTS <2 x s32>,p0,<2 x s1>,s32
fallback1legalize: G_XOR <4 x s8>
fallback1legalize: G_AND <2 x s16>

Gone in new run (28):

KindCountCategory
fallback105legalize: G_UREM <4 x s32>
fallback5legalize: G_MUL <2 x s64>
fallback5legalize: G_UDIV <4 x s32>
fallback4translate: icmp <vscale x 1 x i1>
fallback3legalize: G_SDIV <2 x s64>
fallback2legalize: G_OR <16 x s16>
fallback2translate: lshr <vscale x 4 x i32>
fallback2legalize: G_SREM <2 x s64>
fallback2legalize: G_XOR <2 x s16>
fallback2legalize: G_SREM <4 x s8>
fallback2legalize: G_UDIV <16 x s32>
fallback2translate: icmp <vscale x 2 x i32>
fallback2translate: extractelement <vscale x 16 x i8>
fallback2translate: urem <vscale x 1 x i64>
fallback2translate: sdiv <vscale x 2 x i32>
fallback1legalize: G_INTRINSIC_W_SIDE_EFFECTS <4 x s8>,p0,<4 x s1>,s64,s8
fallback1select: G_STORE s64,p0,s32
fallback1legalize: G_EXTRACT_VECTOR_ELT s32,<16 x s32>,s64
fallback1legalize: G_FREM s128
fallback1legalize: G_FSUB <32 x s16>
fallback1legalize: G_INSERT_VECTOR_ELT <4 x s8>,s8,s64
fallback1legalize: G_EXTRACT s64,s96
fallback1legalize: G_FMUL <2 x s32>
fallback1legalize: G_FDIV s128
fallback1legalize: G_FSUB <32 x s32>
fallback1legalize: G_SEXTLOAD s64,p10,s32
fallback1legalize: G_EXTRACT_VECTOR_ELT s32,<16 x s32>
fallback1translate: fcmp <32 x bfloat>

Count changed (441):

KindOldNewCategory
fallback8122009(+1197)legalize: G_STORE <4 x s1>,p0
fallback1238343(-895)translate: fcmp bfloat
fallback17490(+473)legalize: G_ADD <4 x s32>
fallback517299(-218)legalize: G_FCONSTANT s16
fallback310122(-188)legalize: G_LOAD <8 x s8>,p0
fallback16533(-132)legalize: G_XOR <8 x s8>
fallback13118(+105)legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s32
fallback18118(+100)legalize: G_INSERT_VECTOR_ELT <8 x s8>,s8,s64
fallback21120(+99)legalize: G_ASHR <2 x s64>
fallback954(-91)legalize: G_ASHR <8 x s8>
fallback9118(-73)legalize: G_FDIV <4 x s32>
fallback743(-71)translate: fmul bfloat
fallback656(-59)legalize: G_AND <8 x s8>
fallback1973(+54)legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>,s64
fallback1061(+51)legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>
fallback253(+51)legalize: G_OR <2 x s64>
fallback15201570(+50)legalize: G_STORE <2 x s1>,p0
fallback10871137(+50)unable to lower arguments
fallback177225(+48)legalize: G_FADD s16
fallback6821(-47)legalize: G_FADD <4 x s32>
fallback6619(-47)legalize: G_FMUL <4 x s32>
fallback4183(+42)legalize: G_FSUB <4 x s32>
fallback3375(+42)legalize: G_ASHR <4 x s32>
fallback395358(-37)legalize: G_STORE <8 x s1>,p0
fallback5692(+36)legalize: G_SITOFP s16,s32
fallback4610(-36)legalize: G_FSINH s16
fallback1046(+36)legalize: G_FEXP s16
fallback1651(+35)legalize: G_MUL <8 x s8>
fallback1751(+34)translate: call llvm.experimental.constrained.fptoui.i64.f16
fallback9056(-34)legalize: G_FMA s16
fallback4275(+33)legalize: G_AND <2 x s64>
fallback6432(-32)translate: call llvm.experimental.constrained.ceil.f16
fallback10472(-32)legalize: G_FMINIMUM s32
fallback1648(+32)translate: call llvm.experimental.constrained.round.f16
fallback3466(+32)legalize: G_UMULH s64
fallback9968(-31)legalize: G_FNEG s16
fallback1141(+30)translate: fdiv bfloat
fallback432(+28)legalize: G_SDIV <8 x s8>
fallback186158(-28)legalize: G_CLMUL s16
fallback4517(-28)legalize: G_SREM <4 x s32>
fallback2856(+28)legalize: G_LSHR <2 x s128>
fallback2448(+24)translate: fptrunc float
fallback3814(-24)legalize: G_SDIV <4 x s32>
fallback4016(-24)legalize: G_STRICT_FMUL s16
fallback4064(+24)legalize: G_FFREXP s16,s32
fallback2347(+24)legalize: G_EXTRACT_VECTOR_ELT s8,<8 x s8>,s64
fallback4062(+22)legalize: G_FMUL s16
fallback3311(-22)legalize: G_CTLZ_ZERO_POISON s32,s128
fallback2041(+21)legalize: G_LOAD <2 x s32>,p0
fallback6241(-21)legalize: G_FSUB s16
crash509488(-21)Assertion failed: (BestRC && "Couldn't find the register class"), function getCommonMinimalPhysRegClass, file TargetRegisterInfo.cpp
fallback104124(+20)legalize: G_INTRINSIC_ROUND s16
fallback244(-20)legalize: G_SHL <4 x s32>
fallback2343(+20)legalize: G_EXTRACT_VECTOR_ELT s8,<8 x s8>,s32
fallback4866(+18)legalize: G_CLMUL s4
fallback1230(+18)legalize: G_XOR <4 x s32>
fallback2810(-18)legalize: G_FTAN s16
fallback2810(-18)legalize: G_FEXP2 s16
fallback1028(+18)legalize: G_FCOSH s16
fallback6078(+18)legalize: G_STRICT_FMA s32
fallback7456(-18)legalize: G_FMINIMUM s16
fallback6078(+18)legalize: G_STRICT_FMA s64
fallback3417(-17)translate: call llvm.experimental.constrained.uitofp.f16.i64
fallback1734(+17)translate: call llvm.experimental.constrained.fptrunc.f16.f64
fallback167184(+17)legalize: G_LOAD <4 x s32>,p0
fallback133150(+17)translate: call
fallback6851(-17)translate: call llvm.experimental.constrained.sitofp.f16.i16
fallback1734(+17)translate: call llvm.experimental.constrained.fptoui.i16.f16
fallback181(-17)legalize: G_UDIV <8 x s8>
fallback3417(-17)translate: call llvm.experimental.constrained.fpext.f32.f16
fallback1734(+17)translate: call llvm.experimental.constrained.fptrunc.f16.f128
fallback3147(+16)legalize: G_LSHR <4 x s32>
fallback1632(+16)translate: call llvm.experimental.constrained.llround.i64.f16
fallback3115(-16)legalize: G_SUB <2 x s64>
fallback824(+16)translate: call llvm.experimental.constrained.lround.i32.f16
fallback3248(+16)translate: call llvm.experimental.constrained.sitofp.f64.i32
fallback3248(+16)legalize: G_FMAXIMUM s32
fallback3248(+16)legalize: G_STRICT_FLDEXP s16,s32
fallback4832(-16)translate: call llvm.experimental.constrained.nearbyint.f16
fallback1632(+16)translate: call llvm.experimental.constrained.floor.f16
fallback3216(-16)translate: call llvm.experimental.constrained.trunc.f16
fallback824(+16)translate: call llvm.experimental.constrained.lround.i64.f16
fallback2641(+15)legalize: G_ADD <8 x s8>
fallback3521(-14)legalize: G_VAARG s64,p0
fallback2814(-14)legalize: G_FPTRUNC s16,s128
fallback2410(-14)legalize: G_FMINNUM s16
fallback4862(+14)legalize: G_FSIN s16
fallback3925(-14)legalize: G_SUB <4 x s16>
fallback620(+14)legalize: G_FMAXIMUMNUM s16
fallback4862(+14)legalize: G_FPTOUI_SAT s32,s64
fallback7662(-14)legalize: G_ATOMICRMW_NAND s32,p0
fallback2640(+14)legalize: G_FMAXIMUM s16
fallback10996(-13)translate: call llvm.experimental.constrained.uitofp.f16.i32
fallback4229(-13)legalize: G_SREM <4 x s16>
fallback6250(-12)legalize: G_LOAD <2 x s64>,p0
fallback2412(-12)legalize: G_STRICT_FMUL s32
fallback1224(+12)translate: call llvm.experimental.constrained.maxnum.f64
fallback108120(+12)legalize: G_STRICT_FCMPS s1,s64
fallback3648(+12)legalize: G_CLMUL s128
fallback108120(+12)legalize: G_STRICT_FCMPS s1,s32
fallback1224(+12)translate: call llvm.experimental.constrained.maxnum.f32
fallback5062(+12)legalize: G_FPTRUNC s16,s64
fallback1830(+12)translate: fptrunc double
fallback3119(-12)legalize: G_BITCAST s64,<2 x s32>
fallback113(+12)legalize: G_SREM <8 x s8>
fallback108120(+12)legalize: G_STRICT_FCMPS s1,s16
fallback2412(-12)legalize: G_STRICT_FMUL s64
fallback3322(-11)legalize: G_FCANONICALIZE <2 x s64>
fallback3322(-11)legalize: G_FCANONICALIZE <2 x s16>
fallback2233(+11)legalize: G_FCANONICALIZE <4 x s16>
fallback2233(+11)legalize: G_FCANONICALIZE <2 x s32>
fallback1020(+10)legalize: G_FLDEXP s16,s32
fallback4838(-10)translate: call llvm.experimental.constrained.uitofp.f64.i32
fallback8272(-10)legalize: G_INTRINSIC p0
fallback1020(+10)legalize: G_CLMUL s48
fallback4757(+10)legalize: G_FABS s16
fallback7585(+10)legalize: G_CLMUL s64
fallback2939(+10)legalize: G_FDIV s16
fallback3242(+10)translate: call llvm.experimental.constrained.sitofp.f32.i32
fallback116126(+10)legalize: G_FPTOUI_SAT s32,s16
fallback3242(+10)legalize: G_ATOMIC_CMPXCHG s32,p0
fallback2010(-10)legalize: G_SITOFP s128,s64
fallback211(+9)legalize: G_SHL <2 x s64>
fallback211(+9)legalize: G_FMUL s128
fallback6271(+9)translate: call llvm.experimental.constrained.fptoui.i32.f16
fallback3223(-9)legalize: G_FCANONICALIZE s32
fallback244235(-9)select: G_GLOBAL_VALUE p0
fallback10192(-9)translate: call llvm.experimental.constrained.sitofp.f16.i32
fallback3224(-8)legalize: G_STRICT_FSQRT s16
fallback3947(+8)legalize: G_INVOKE_REGION_START
fallback4840(-8)legalize: G_FPTOSI_SAT s32,s64
fallback816(+8)legalize: G_STRICT_FADD s16
fallback412(+8)legalize: G_SREM <4 x s64>
fallback8694(+8)legalize: G_INTRINSIC_TRUNC s16
fallback140148(+8)legalize: G_STRICT_FCMP s1,s16
fallback412(+8)legalize: G_SUB <4 x s64>
fallback8678(-8)legalize: G_FPTOUI_SAT s64,s16
fallback816(+8)legalize: G_STRICT_FSUB s16
fallback7987(+8)legalize: G_INTRINSIC s64
fallback92100(+8)legalize: G_INTRINSIC_ROUNDEVEN s16
fallback2230(+8)translate: fadd bfloat
fallback7078(+8)legalize: G_FPTOSI_SAT s64,s16
fallback7078(+8)legalize: G_BLOCK_ADDR p0
fallback2820(-8)select: G_PREFETCH p0
fallback4048(+8)legalize: G_LOAD <16 x s8>,p0
fallback124(-8)silent fallback (no remark emitted)
fallback104112(+8)legalize: G_STRICT_FMA s16
fallback122114(-8)legalize: G_FPTOSI_SAT s32,s16
fallback147(-7)legalize: G_UMULH s8
fallback1219(+7)legalize: G_ATOMICRMW_UMIN s64,p0
fallback512(+7)legalize: G_LSHR <4 x s16>
fallback125(-7)legalize: G_XOR <2 x s64>
fallback512(+7)translate: frem bfloat
fallback158(-7)legalize: G_SMULH s16
fallback1118(+7)legalize: G_BITCAST s64,<4 x s16>
fallback3528(-7)legalize: G_SUB <8 x s8>
fallback613(+7)legalize: G_EXTRACT_VECTOR_ELT s16,<2 x s16>,s64
fallback613(+7)legalize: G_UREM <4 x s16>
fallback126(-6)translate: call llvm.experimental.constrained.exp2.f32
fallback612(+6)translate: call llvm.experimental.constrained.trunc.f32
fallback5460(+6)legalize: G_INTRINSIC s32,<2 x s16>
fallback126(-6)legalize: G_STRICT_FDIV s32
fallback126(-6)translate: call llvm.experimental.constrained.fptosi.i64.f32
fallback612(+6)translate: call llvm.experimental.constrained.powi.f64
fallback612(+6)translate: call llvm.experimental.constrained.llround.i64.f64
fallback126(-6)translate: call llvm.experimental.constrained.tanh.f32
fallback4248(+6)legalize: G_VAARG s32,p0
fallback126(-6)legalize: G_STRICT_FDIV s64
fallback1812(-6)translate: call llvm.experimental.constrained.uitofp.f32.i16
fallback612(+6)translate: call llvm.experimental.constrained.fptosi.i64.f64
fallback1824(+6)legalize: G_ATOMICRMW_XCHG s32,p0
fallback2418(-6)translate: call llvm.experimental.constrained.minnum.f64
fallback2014(-6)legalize: G_BITCAST s64,<8 x s8>
fallback1218(+6)translate: call llvm.experimental.constrained.uitofp.f64.i64
fallback1812(-6)translate: call llvm.experimental.constrained.nearbyint.f64
fallback126(-6)translate: call llvm.experimental.constrained.tanh.f64
fallback126(-6)translate: call llvm.experimental.constrained.acos.f64
fallback126(-6)translate: call llvm.experimental.constrained.acos.f32
fallback126(-6)translate: call llvm.experimental.constrained.uitofp.f64.i16
fallback5650(-6)legalize: G_OR <8 x s8>
fallback612(+6)translate: call llvm.experimental.constrained.llround.i64.f32
fallback1812(-6)translate: call llvm.experimental.constrained.sitofp.f32.i128
fallback2418(-6)translate: call llvm.experimental.constrained.minnum.f32
fallback1824(+6)legalize: G_UREM <8 x s8>
fallback1824(+6)translate: sitofp i32
fallback612(+6)translate: call llvm.experimental.constrained.trunc.f64
fallback612(+6)translate: call llvm.experimental.constrained.asin.f32
fallback612(+6)translate: call llvm.experimental.constrained.fpext.f64.f32
fallback612(+6)legalize: G_STRICT_FSUB s32
fallback410(+6)legalize: G_EXTRACT_VECTOR_ELT s16,<2 x s16>,s32
fallback410(+6)legalize: G_FPTOUI_SAT s8,s32
fallback612(+6)translate: call llvm.experimental.constrained.roundeven.f32
fallback104(-6)legalize: G_FPTOSI_SAT s16,s64
fallback410(+6)legalize: G_FPTOSI_SAT s8,s64
fallback126(-6)translate: call llvm.experimental.constrained.exp2.f64
fallback3327(-6)legalize: G_FFREXP s128,s32
fallback1812(-6)legalize: G_STORE <3 x s33>,p0
fallback612(+6)translate: call llvm.experimental.constrained.floor.f64
fallback1812(-6)translate: call llvm.experimental.constrained.uitofp.f64.i8
fallback126(-6)translate: call llvm.experimental.constrained.rint.f64
fallback612(+6)translate: call llvm.experimental.constrained.roundeven.f64
fallback1824(+6)translate: uitofp i32
fallback2531(+6)legalize: G_INTRINSIC_W_SIDE_EFFECTS
fallback612(+6)translate: call llvm.experimental.constrained.powi.f32
fallback410(+6)legalize: G_VECREDUCE_ADD s16,<16 x s16>
fallback612(+6)translate: call llvm.experimental.constrained.asin.f64
fallback1218(+6)translate: call llvm.experimental.constrained.uitofp.f32.i8
fallback1812(-6)translate: call llvm.experimental.constrained.nearbyint.f32
fallback1812(-6)translate: uitofp i16
fallback612(+6)translate: call llvm.experimental.constrained.sitofp.f32.i64
fallback126(-6)translate: call llvm.experimental.constrained.rint.f32
fallback2418(-6)legalize: G_RESET_FPENV
fallback108102(-6)legalize: G_FCEIL s16
fallback612(+6)translate: call llvm.experimental.constrained.floor.f32
fallback612(+6)legalize: G_STRICT_FSUB s64
fallback1812(-6)translate: call llvm.experimental.constrained.sitofp.f16.i128
fallback1812(-6)translate: call llvm.experimental.constrained.sitofp.f64.i128
fallback3642(+6)legalize: G_FFREXP s64,s32
fallback2520(-5)legalize: G_LSHR <8 x s8>
fallback185190(+5)legalize: G_IMPLICIT_DEF <2 x s16>
fallback5459(+5)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0
crash8883(-5)Assertion failed: (VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 && "unexpected custom value"), function int, file RISCVCallLowering.cpp
fallback27(+5)legalize: G_UITOFP s16,s128
fallback2621(-5)legalize: G_LSHR <2 x s64>
fallback711(+4)legalize: G_INTRINSIC s32,<4 x s8>
crash1612(-4)Assertion failed: (DstTy.isVector() && SrcVecTy.isVector() && "Extract subvector VTs must be vectors!"), function buildInstr, file MachineIRBuilder.cpp
fallback1612(-4)legalize: G_ATOMIC_CMPXCHG s64,p0
fallback4945(-4)translate: call llvm.experimental.constrained.fptoui.i32.f32
crash128(-4)Assertion failed: (getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag"), function lowerInlineAsm, file InlineAsmLowering.cpp
fallback1713(-4)legalize: G_STRICT_FADD s64
fallback711(+4)translate: call llvm.is.fpclass.nxv4f32
fallback84(-4)legalize: G_FPTOUI_SAT s16,s32
fallback4844(-4)legalize: G_FPTOSI_SAT s32
fallback8884(-4)legalize: G_INTRINSIC_W_SIDE_EFFECTS s32,p0
fallback37(+4)legalize: G_INSERT_VECTOR_ELT <4 x s32>,s32
fallback2622(-4)legalize: G_ATOMICRMW_ADD s32,p0
fallback3438(+4)legalize: G_INSERT_SUBVECTOR <vscale x 4 x s16>,<8 x s16>
fallback128132(+4)legalize: G_STRICT_FCMP s1,s32
fallback2024(+4)legalize: G_FMAXIMUM s64
fallback610(+4)legalize: G_FSINCOS s64
fallback4036(-4)legalize: G_FMINIMUM s64
fallback4044(+4)legalize: G_LOAD <8 x s16>,p0
fallback610(+4)legalize: G_INSERT_SUBVECTOR <vscale x 1 x s32>,<2 x s32>
fallback128(-4)legalize: G_SEXTLOAD s256,p0,s128
fallback3430(-4)legalize: G_ATOMICRMW_SUB s32,p0
fallback48(+4)legalize: G_ATOMICRMW_ADD s16,p0
fallback1418(+4)legalize: G_FPTOSI_SAT s8,s16
fallback26(+4)legalize: G_VECREDUCE_OR s32,<4 x s32>
fallback3034(+4)legalize: G_SET_ROUNDING s32
fallback8985(-4)legalize: G_FCANONICALIZE s64
fallback48(+4)legalize: G_INTRINSIC_W_SIDE_EFFECTS p0,s32
fallback26(+4)select: G_INTRINSIC_W_SIDE_EFFECTS <vscale x 4 x s32>,s64
fallback7975(-4)translate: call llvm.experimental.constrained.fptosi.i32.f16
crash84(-4)Assertion failed: (DstTy.getElementType() == SrcVecTy.getElementType() && "Extract subvector VTs must have the same element type!"), function buildInstr, file MachineIRBuilder.cpp
fallback1014(+4)legalize: G_INSERT_SUBVECTOR <vscale x 8 x s8>,<16 x s8>
fallback26(+4)legalize: G_SMULH s8
fallback1612(-4)legalize: G_BITCAST s32,<4 x s8>
fallback812(+4)legalize: G_STORE <3 x s1>,p0
fallback36(+3)translate: call llvm.experimental.constrained.lrint.i32.f64
fallback1411(-3)legalize: G_ATOMICRMW_UMIN s64,p0,s32
fallback7976(-3)legalize: G_INTRINSIC_W_SIDE_EFFECTS s64,p0,s32
fallback36(+3)legalize: G_SET_FPENV s64
fallback47(+3)legalize: G_SELECT <4 x s64>,<4 x s1>
fallback96(-3)translate: call llvm.experimental.constrained.fptosi.i128.f16
fallback85(-3)legalize: G_FSINCOS s128
fallback25(+3)legalize: G_LSHR <4 x s64>
fallback36(+3)translate: call llvm.experimental.constrained.lrint.i32.f32
fallback96(-3)translate: call llvm.experimental.constrained.fptosi.i128.f64
fallback36(+3)legalize: G_SET_FPENV s32
fallback1411(-3)legalize: G_ATOMICRMW_UMIN s32,p0
fallback4239(-3)legalize: G_ADD <4 x s16>
fallback74(-3)legalize: G_LSHR <2 x s32>
fallback912(+3)translate: call llvm.experimental.constrained.fptoui.i128.f32
fallback41(-3)legalize: G_OR <4 x s32>
fallback4441(-3)legalize: G_INTRINSIC s64,<2 x s32>
fallback912(+3)translate: call llvm.experimental.constrained.fptoui.i128.f64
fallback36(+3)translate: call llvm.experimental.constrained.lrint.i64.f64
fallback1114(+3)select: G_JUMP_TABLE p0
fallback4845(-3)legalize: G_CLMUL s32
fallback1114(+3)legalize: G_ATOMICRMW_MIN s32,p0
fallback1114(+3)legalize: G_ATOMICRMW_MIN s64,p0,s32
fallback1714(-3)legalize: G_ZEXTLOAD s256,p0,s128
fallback118(-3)legalize: G_UREM <2 x s64>
fallback912(+3)translate: call llvm.experimental.constrained.fptoui.i128.f16
fallback36(+3)translate: call llvm.experimental.constrained.lrint.i64.f32
fallback96(-3)translate: call llvm.experimental.constrained.fptosi.i128.f32
fallback1214(+2)legalize: G_ATOMICRMW_MAX s64,p0
fallback9795(-2)legalize: G_FPTRUNC s16,s32
fallback4850(+2)translate: call llvm.experimental.constrained.uitofp.f32.i32
fallback24(+2)legalize: G_ASHR <4 x s8>
fallback64(-2)legalize: G_SMULH s4
fallback35(+2)translate: call llvm.fabs.nxv4f32
fallback810(+2)legalize: G_SMULH s64
fallback2426(+2)legalize: G_LOAD <4 x s16>,p0
fallback1315(+2)legalize: G_ATOMICRMW_MAX s64,p0,s32
fallback24(+2)legalize: G_UMULH s13
fallback64(-2)legalize: G_FMAXIMUM s128
fallback46(+2)legalize: G_UMULH <4 x s16>
fallback6668(+2)legalize: G_ATOMICRMW_OR s32,p0
fallback2628(+2)legalize: G_CLMUL <2 x s64>

Generated 2026-10-15 08:05 UTC.