fallback: legalize: G_AND <8 x s8>

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_AND <8 x s8>
Occurrences:56 in 43 configs, 12 test files
Snippet from:rvp-simd-64.ll @test_and_b via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <8 x i8> @test_and_b(<8 x i8> %a, <8 x i8> %b) {
  %res = and <8 x i8> %a, %b
  ret <8 x i8> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<8 x s8>) = G_AND %0:_, %1:_ (in function: test_and_b)
warning: Instruction selection used fallback path for test_and_b

Occurrences (56) (first 50):

InputFunctionConfig
rvp-simd-64.lltest_and_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_andn_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
alu32.c07337ea51.ll (mutant of alu32.ll)srli-mtriple=riscv64 -verify-machineinstrs
alu32.fe4a731642.ll (mutant of alu32.ll)srli-mtriple=riscv32 -verify-machineinstrs
atomic-signext.398eb542f9.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv32 -mattr=+a -verify-machineinstrs
atomic-signext.4976e1f672.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv32 -verify-machineinstrs
atomic-signext.57569e4f96.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv64 -mattr=+a,+zacas -verify-machineinstrs
atomic-signext.6072554072.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs
atomic-signext.7dbcc4cf5c.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv64 -verify-machineinstrs
atomic-signext.a78041d744.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv64 -mattr=+a -verify-machineinstrs
atomic-signext.cbe4a023ec.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs
atomic-signext.e540138bcc.ll (mutant of atomic-signext.ll)atomicrmw_xor_i8_monotonic-mtriple=riscv32 -mattr=+a,+zacas -verify-machineinstrs
compress-opt-select.d1abaca8b9.ll (mutant of compress-opt-select.ll)ne_medium_neg-mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -M no-aliases
compress-opt-select.d428afd074.ll (mutant of compress-opt-select.ll)ne_medium_neg-mtriple=riscv32 -target-abi ilp32d -mattr=+zca,+f,+d -M no-aliases
compress-opt-select.e45f76e3f6.ll (mutant of compress-opt-select.ll)ne_medium_neg-mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -M no-aliases
ctlz-cttz-ctpop.075410f467.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv32 -verify-machineinstrs
ctlz-cttz-ctpop.08e2f5c619.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv64 -mattr=+xtheadbb -verify-machineinstrs
ctlz-cttz-ctpop.8c17a45864.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv32 -mattr=+m -verify-machineinstrs
ctlz-cttz-ctpop.8fb20abd04.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv64 -mattr=+m -verify-machineinstrs
ctlz-cttz-ctpop.b175b84782.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv32 -mattr=+xtheadbb -verify-machineinstrs
ctlz-cttz-ctpop.e093b343e0.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv64 -mattr=+zbb -verify-machineinstrs
ctlz-cttz-ctpop.f4473b87fa.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv64 -verify-machineinstrs
ctlz-cttz-ctpop.fdd6cfd425.ll (mutant of ctlz-cttz-ctpop.ll)test_cttz_i64_zero_poison-mtriple=riscv32 -mattr=+zbb -verify-machineinstrs
div-by-constant.597015a1b0.ll (mutant of div-by-constant.ll)udiv16_constant_add-mtriple=riscv32 -mattr=+m,+zba,+zbb -verify-machineinstrs
div-by-constant.68781e8091.ll (mutant of div-by-constant.ll)udiv16_constant_add-mtriple=riscv64 -mattr=+m,+zba,+zbb -verify-machineinstrs
div-by-constant.a5990681aa.ll (mutant of div-by-constant.ll)udiv16_constant_add-mtriple=riscv32 -mattr=+m -verify-machineinstrs
div-by-constant.e2527a7bbb.ll (mutant of div-by-constant.ll)udiv16_constant_add-mtriple=riscv64 -mattr=+m -verify-machineinstrs
half-arith.1024de670e.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv32 -verify-machineinstrs
half-arith.1ccb59a0e0.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f
half-arith.2df021bfcb.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi ilp32
half-arith.35d5e040a3.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64
half-arith.638539ae68.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.655f632569.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv64 -verify-machineinstrs
half-arith.6fddcf009b.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f
half-arith.bdc5ad8fe3.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32
half-arith.ef63c97632.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.f65b3af509.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64
inline-asm-abi-names.f6840f62b2.ll (mutant of inline-asm-abi-names.ll)explicit_register_tp-mtriple=riscv64 -verify-machineinstrs -no-integrated-as
inline-asm-abi-names.fd66896de8.ll (mutant of inline-asm-abi-names.ll)explicit_register_tp-mtriple=riscv32 -verify-machineinstrs -no-integrated-as
mul-expand.445f949147.ll (mutant of mul-expand.ll)muli64_0x0fffffff-mtriple=riscv32 -verify-machineinstrs
mul-expand.d9996b13db.ll (mutant of mul-expand.ll)muli64_0x0fffffff-mtriple=riscv64 -verify-machineinstrs
musttail-indirect-args.166323ecef.ll (mutant of musttail-indirect-args.ll)caller_musttail_two_indirect_swapped-mtriple=riscv64
musttail-indirect-args.5b9ce406be.ll (mutant of musttail-indirect-args.ll)caller_musttail_two_indirect_swapped-mtriple=riscv32
select-cond.07d151af8a.ll (mutant of select-cond.ll)select_i32_ule-mtriple=riscv32 -verify-machineinstrs
select-cond.41bc3a215d.ll (mutant of select-cond.ll)select_i32_ule-mtriple=riscv32 -mattr=+xqcicm -verify-machineinstrs
select-cond.9beea5c957.ll (mutant of select-cond.ll)select_i32_ule-mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs
select-cond.b275ec7a2b.ll (mutant of select-cond.ll)select_i32_ule-mtriple=riscv32 -mattr=+xtheadcondmov -verify-machineinstrs
select-cond.dfd6a2e2fe.ll (mutant of select-cond.ll)select_i32_ule-mtriple=riscv64 -verify-machineinstrs
select-cond.e50e5ca8d5.ll (mutant of select-cond.ll)select_i32_ule-mtriple=riscv32 -mattr=+xqcics -verify-machineinstrs
select-cond.f0d870aa30.ll (mutant of select-cond.ll)select_i32_ule-mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.