fallback: legalize: G_BUILD_VECTOR <2 x s32>,s32

Run:	explore-04ca53e65f-20261014-114124
Kind:	fallback
Category:	legalize: G_BUILD_VECTOR <2 x s32>,s32
Occurrences:	13 in 1 configs, 2 test files
Snippet from:	rvp-simd-64.ll @test_pli_h_v2i32 via llvm-extract
Config:	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define <2 x i32> @test_pli_h_v2i32() {
  ret <2 x i32> splat (i32 6553700)
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %0:_(<2 x s32>) = G_BUILD_VECTOR %1:_(s32), %1:_(s32) (in function: test_pli_h_v2i32)
warning: Instruction selection used fallback path for test_pli_h_v2i32

Occurrences (13):

Input	Function	Config
rvp-insert-subvector.ll	insert_zero_v1i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_pli_h_v2i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_pli_b_v2i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_pli_w	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_plui_h_v2i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_plui_h_negative_v2i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_plui_w	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_plui_w_negative	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_allones_v2i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_build_vector_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_return_zero	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-insert-subvector.5ee2ad1442.ll (mutant of rvp-insert-subvector.ll)	insert_zero_v1i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.bbbe9772a2.ll (mutant of rvp-simd-64.ll)	test_plui_w	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.