fallback: legalize: G

fallback: legalize: G_CLMUL s32

Run:	explore-04ca53e65f-20261014-114124
Kind:	fallback
Category:	legalize: G_CLMUL s32
Occurrences:	35 in 12 configs, 5 test files
Snippet from:	combine-clmul.ll @combine_i32_cmul_constant via llvm-extract
Config:	`-mtriple=riscv64 -mattr=+zbc`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i32 @combine_i32_cmul_constant() #0 {
  %res = call i32 @llvm.clmul.i32(i32 6, i32 10)
  ret i32 %res
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.clmul.i32(i32, i32) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv64 -mattr=+zbc -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+zbc -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_CLMUL %0:_, %1:_ (in function: combine_i32_cmul_constant)
warning: Instruction selection used fallback path for combine_i32_cmul_constant

Occurrences (35):

Input	Function	Config
clmul.ll	clmul_i32	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv32 -mattr=+m,+zbs -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv32 -mattr=+m,+zvbc -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv32 -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv64 -mattr=+m,+zbc -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv64 -mattr=+m,+zbs -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv64 -mattr=+m,+zvbc -verify-machineinstrs`
clmul.ll	clmul_i32	`-mtriple=riscv64 -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv32 -mattr=+m,+zbs -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv32 -mattr=+m,+zvbc -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv32 -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv64 -mattr=+m,+zbc -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv64 -mattr=+m,+zbs -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv64 -mattr=+m,+zvbc -verify-machineinstrs`
clmulh.ll	clmulh_i16	`-mtriple=riscv64 -verify-machineinstrs`
clmulr.ll	clmulr_i16	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
clmulr.ll	clmulr_i16	`-mtriple=riscv32 -mattr=+m,+zbs -verify-machineinstrs`
clmulr.ll	clmulr_i16	`-mtriple=riscv32 -verify-machineinstrs`
clmulr.ll	clmulr_i16	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
clmulr.ll	clmulr_i16	`-mtriple=riscv64 -mattr=+m,+zbc -verify-machineinstrs`
clmulr.ll	clmulr_i16	`-mtriple=riscv64 -mattr=+m,+zbs -verify-machineinstrs`
clmulr.ll	clmulr_i16	`-mtriple=riscv64 -verify-machineinstrs`
combine-clmul.ll	combine_i32_cmul_constant	`-mtriple=riscv64 -mattr=+zbc`
combine-clmul.ll	combine_i32_cmul_zero	`-mtriple=riscv64 -mattr=+zbc`
rv64zbc-zbkc-intrinsic.ll	clmul32	`-mtriple=riscv64 -mattr=+zbc -verify-machineinstrs`
rv64zbc-zbkc-intrinsic.ll	llvm_clmul_i32	`-mtriple=riscv64 -mattr=+zbc -verify-machineinstrs`
rv64zbc-zbkc-intrinsic.ll	clmul32	`-mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs`
rv64zbc-zbkc-intrinsic.ll	llvm_clmul_i32	`-mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs`
combine-clmul.d2ab188436.ll (mutant of combine-clmul.ll)	combine_i32_cmul_zero	`-mtriple=riscv64 -mattr=+zbc`
combine-clmul.ee6f6f7e10.ll (mutant of combine-clmul.ll)	combine_i32_cmul_zero	`-mtriple=riscv64 -mattr=+zbc`
rv64zbc-zbkc-intrinsic.2b8a2265bd.ll (mutant of rv64zbc-zbkc-intrinsic.ll)	clmul32	`-mtriple=riscv64 -mattr=+zbc -verify-machineinstrs`
rv64zbc-zbkc-intrinsic.4853ddd371.ll (mutant of rv64zbc-zbkc-intrinsic.ll)	clmul32	`-mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.