fallback: legalize: G_EXTRACT_VECTOR

fallback: legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>,s64

Run:	explore-04ca53e65f-20261014-114124
Kind:	fallback
Category:	legalize: G_EXTRACT_VECTOR_ELT s32,<4 x s32>,s64
Occurrences:	23 in 9 configs, 6 test files
Snippet from:	reduction-formation.ll @reduce_sum_4xi32 via llvm-extract
Config:	`-mtriple=riscv64 -verify-machineinstrs`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define i32 @reduce_sum_4xi32(<4 x i32> %v) {
  %e0 = extractelement <4 x i32> %v, i32 0
  %e1 = extractelement <4 x i32> %v, i32 1
  %e2 = extractelement <4 x i32> %v, i32 2
  %e3 = extractelement <4 x i32> %v, i32 3
  %add0 = add i32 %e0, %e1
  %add1 = add i32 %add0, %e2
  %add2 = add i32 %add1, %e3
  ret i32 %add2
}

Reproduce:

llc -mtriple=riscv64 -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %8:_(s32) = G_EXTRACT_VECTOR_ELT %0:_(<4 x s32>), %9:_(s64) (in function: reduce_sum_4xi32)
warning: Instruction selection used fallback path for reduce_sum_4xi32

Occurrences (23):

Input	Function	Config
combine-is_fpclass.ll	extract_bitcast_sign_set_not_pos	`-mtriple=riscv64 -mattr=+v,+f,+d`
combine-is_fpclass.ll	extract_bitcast_unknown_sign_ispos	`-mtriple=riscv64 -mattr=+v,+f,+d`
combine-is_fpclass.ll	extract_bitcast_not_nan	`-mtriple=riscv64 -mattr=+v,+f,+d`
combine-is_fpclass.ll	extract_bitcast_maybe_nan	`-mtriple=riscv64 -mattr=+v,+f,+d`
combine-is_fpclass.ll	extract_bitcast_unknown_idx_not_pos	`-mtriple=riscv64 -mattr=+v,+f,+d`
combine-is_fpclass.ll	extract_fabs_unknown_idx_isneg	`-mtriple=riscv64 -mattr=+v,+f,+d`
double_reduct.ll	fmul_f32	`-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs`
double_reduct.ll	mul_i32	`-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs`
reduction-formation.ll	reduce_sum_4xi32	`-mtriple=riscv64 -verify-machineinstrs`
reduction-formation.ll	reduce_xor_4xi32	`-mtriple=riscv64 -verify-machineinstrs`
reduction-formation.ll	reduce_or_4xi32	`-mtriple=riscv64 -verify-machineinstrs`
double_reduct.99f0dfee30.ll (mutant of double_reduct.ll)	fmul_f32	`-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs`
forced-atomics.302cbe6b33.ll (mutant of forced-atomics.ll)	rmw64_add_seq_cst	`-mtriple=riscv64`
forced-atomics.73b00f7520.ll (mutant of forced-atomics.ll)	rmw64_add_seq_cst	`-mtriple=riscv64 -mattr=+forced-atomics`
forced-atomics.8c0e8588c1.ll (mutant of forced-atomics.ll)	rmw64_add_seq_cst	`-mtriple=riscv64 -mattr=+no-trailing-seq-cst-fence`
forced-atomics.cb5a096941.ll (mutant of forced-atomics.ll)	rmw64_add_seq_cst	`-mtriple=riscv64 -mattr=+forced-atomics,+no-trailing-seq-cst-fence`
inline-asm-d-abi-names.076d3f27a6.ll (mutant of inline-asm-d-abi-names.ll)	explicit_register_fs5	`-mtriple=riscv64 -mattr=+f,+d -target-abi lp64d -verify-machineinstrs`
inline-asm-f-abi-names.2815ebcd1b.ll (mutant of inline-asm-f-abi-names.ll)	explicit_register_fs5	`-mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs`
reduction-formation.1162322859.ll (mutant of reduction-formation.ll)	reduce_sum_4xi32	`-mtriple=riscv64 -verify-machineinstrs`
reduction-formation.1162322859.ll (mutant of reduction-formation.ll)	reduce_xor_4xi32	`-mtriple=riscv64 -verify-machineinstrs`
reduction-formation.5e16fd769a.ll (mutant of reduction-formation.ll)	reduce_or_4xi32	`-mtriple=riscv64 -verify-machineinstrs`
reduction-formation.896a85fffd.ll (mutant of reduction-formation.ll)	reduce_xor_4xi32	`-mtriple=riscv64 -verify-machineinstrs`
reduction-formation.ed04c7e778.ll (mutant of reduction-formation.ll)	reduce_sum_4xi32	`-mtriple=riscv64 -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.