fallback: legalize: G_FPTOSI_SAT s64,s32

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_FPTOSI_SAT s64,s32
Occurrences:42 in 6 configs, 2 test files
Snippet from:float-convert.ll @fcvt_l_s_sat via llvm-extract
Config:-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i64 @fcvt_l_s_sat(float %a) #0 {
start:
  %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
  ret i64 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.fptosi.sat.i64.f32(float) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s64) = G_FPTOSI_SAT %0:_(s32) (in function: fcvt_l_s_sat)
warning: Instruction selection used fallback path for fcvt_l_s_sat

Occurrences (42):

InputFunctionConfig
float-convert.llfcvt_l_s_sat-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.llfcvt_l_s_sat-mtriple=riscv32 -verify-machineinstrs
float-convert.llfcvt_l_s_sat-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-convert.llfcvt_l_s_sat-mtriple=riscv64 -verify-machineinstrs
float-round-conv-sat.lltest_floor_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_ceil_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_trunc_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_round_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_roundeven_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_rint_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_floor_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_ceil_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_trunc_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_round_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_roundeven_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_rint_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_floor_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_ceil_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_trunc_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_round_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_roundeven_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_rint_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_floor_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_ceil_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_trunc_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_round_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_roundeven_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_rint_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-convert.26c5a39ec2.ll (mutant of float-convert.ll)fcvt_l_s_sat-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-convert.a1e36b7b50.ll (mutant of float-convert.ll)fcvt_l_s_sat-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.ae32207dd1.ll (mutant of float-convert.ll)fcvt_l_s_sat-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-convert.c70854e28c.ll (mutant of float-convert.ll)fcvt_l_s_sat-mtriple=riscv64 -verify-machineinstrs
float-convert.c91d2cfbd1.ll (mutant of float-convert.ll)fcvt_l_s_sat-mtriple=riscv32 -verify-machineinstrs
float-convert.d587411a7f.ll (mutant of float-convert.ll)fcvt_l_s_sat-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.1ce0200fc7.ll (mutant of float-round-conv-sat.ll)test_rint_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.390b982317.ll (mutant of float-round-conv-sat.ll)test_rint_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.5299abd889.ll (mutant of float-round-conv-sat.ll)test_floor_si64-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.53b4d6f1fe.ll (mutant of float-round-conv-sat.ll)test_rint_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.6d31da94d8.ll (mutant of float-round-conv-sat.ll)test_floor_si64-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.9040447ab6.ll (mutant of float-round-conv-sat.ll)test_floor_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.ce728e2c41.ll (mutant of float-round-conv-sat.ll)test_floor_si64-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.fbf97b7dff.ll (mutant of float-round-conv-sat.ll)test_rint_si64-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f

Generated 2026-10-15 08:05 UTC.