fallback: legalize: G_FPTOUI_SAT s32

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_FPTOUI_SAT s32
Occurrences:49 in 6 configs, 2 test files
Snippet from:float-convert.ll @fcvt_wu_s_sat via llvm-extract
Config:-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i32 @fcvt_wu_s_sat(float %a) #0 {
start:
  %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
  ret i32 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fptoui.sat.i32.f32(float) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s32) = G_FPTOUI_SAT %0:_(s32) (in function: fcvt_wu_s_sat)
warning: Instruction selection used fallback path for fcvt_wu_s_sat

Occurrences (49):

InputFunctionConfig
float-convert.llfcvt_wu_s_sat-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.llfcvt_wu_s_sat-mtriple=riscv32 -verify-machineinstrs
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv32 -verify-machineinstrs
float-convert.llfcvt_wu_s_sat-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-convert.llfcvt_wu_s_sat-mtriple=riscv64 -verify-machineinstrs
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv64 -verify-machineinstrs
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_round_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_round_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_round_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_round_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-convert.283606e7a4.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.4fc1aeabb5.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-convert.9c9f031c12.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv64 -verify-machineinstrs
float-convert.a11272b375.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-convert.b2c9b4ab07.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv32 -verify-machineinstrs
float-round-conv-sat.054c353f55.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.1ce0200fc7.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.1dd9738b3d.ll (mutant of float-round-conv-sat.ll)test_roundeven_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.390b982317.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.53b4d6f1fe.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.62dc54e813.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.85334c10e1.ll (mutant of float-round-conv-sat.ll)test_roundeven_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.924a33c753.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.af064a112e.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.b380d06c5d.ll (mutant of float-round-conv-sat.ll)test_roundeven_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.ebeb01bd3b.ll (mutant of float-round-conv-sat.ll)test_roundeven_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.fbf97b7dff.ll (mutant of float-round-conv-sat.ll)test_ceil_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f

Generated 2026-10-15 08:05 UTC.