fallback: legalize: G_FPTOUI

fallback: legalize: G_FPTOUI_SAT s32,s64

Run:	explore-04ca53e65f-20261014-114124
Kind:	fallback
Category:	legalize: G_FPTOUI_SAT s32,s64
Occurrences:	56 in 6 configs, 2 test files
Snippet from:	double-convert.ll @fcvt_wu_d_sat via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i32 @fcvt_wu_d_sat(double %a) #0 {
start:
  %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
  ret i32 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fptoui.sat.i32.f64(double) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s32) = G_FPTOUI_SAT %0:_(s64) (in function: fcvt_wu_d_sat)
warning: Instruction selection used fallback path for fcvt_wu_d_sat

Occurrences (56) (first 50):

Input	Function	Config
double-convert.ll	fcvt_wu_d_sat	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-convert.ll	fcvt_wu_d_sat_zext	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-convert.ll	fcvt_wu_d_sat	`-mtriple=riscv32 -verify-machineinstrs`
double-convert.ll	fcvt_wu_d_sat_zext	`-mtriple=riscv32 -verify-machineinstrs`
double-convert.ll	fcvt_wu_d_sat	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-convert.ll	fcvt_wu_d_sat_zext	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-convert.ll	fcvt_wu_d_sat	`-mtriple=riscv64 -verify-machineinstrs`
double-convert.ll	fcvt_wu_d_sat_zext	`-mtriple=riscv64 -verify-machineinstrs`
double-round-conv-sat.ll	test_floor_ui32	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_ceil_ui32	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_trunc_ui32	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_round_ui32	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_roundeven_ui32	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_rint_ui32	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_floor_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_ceil_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_trunc_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_round_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_roundeven_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_rint_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_floor_ui32	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_ceil_ui32	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_trunc_ui32	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_round_ui32	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_roundeven_ui32	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_rint_ui32	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_floor_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_ceil_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_trunc_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_round_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_roundeven_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_rint_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-convert.0347f41702.ll (mutant of double-convert.ll)	fcvt_wu_d_sat	`-mtriple=riscv64 -verify-machineinstrs`
double-convert.12dcf9927e.ll (mutant of double-convert.ll)	fcvt_wu_d_sat_zext	`-mtriple=riscv64 -verify-machineinstrs`
double-convert.24c8d53d98.ll (mutant of double-convert.ll)	fcvt_wu_d_sat_zext	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-convert.4cbd890c21.ll (mutant of double-convert.ll)	fcvt_wu_d_sat	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-convert.4d37570db9.ll (mutant of double-convert.ll)	fcvt_wu_d_sat	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-convert.5e57c4495a.ll (mutant of double-convert.ll)	fcvt_wu_d_sat	`-mtriple=riscv32 -verify-machineinstrs`
double-convert.66268f25e4.ll (mutant of double-convert.ll)	fcvt_wu_d_sat	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-convert.ae941ef2d5.ll (mutant of double-convert.ll)	fcvt_wu_d_sat_zext	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-convert.e31fb36c14.ll (mutant of double-convert.ll)	fcvt_wu_d_sat	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-convert.f192e4a60e.ll (mutant of double-convert.ll)	fcvt_wu_d_sat_zext	`-mtriple=riscv32 -verify-machineinstrs`
double-convert.f4f8b8cb31.ll (mutant of double-convert.ll)	fcvt_wu_d_sat_zext	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-convert.fb47a97595.ll (mutant of double-convert.ll)	fcvt_wu_d_sat_zext	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.15beb0ad6c.ll (mutant of double-round-conv-sat.ll)	test_ceil_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.3d9fc39742.ll (mutant of double-round-conv-sat.ll)	test_ceil_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.443b57c7a1.ll (mutant of double-round-conv-sat.ll)	test_ceil_ui32	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.45b9e1cb78.ll (mutant of double-round-conv-sat.ll)	test_ceil_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.5a7023ec80.ll (mutant of double-round-conv-sat.ll)	test_roundeven_ui32	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.98d336f8c9.ll (mutant of double-round-conv-sat.ll)	test_roundeven_ui32	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`

Generated 2026-10-15 08:05 UTC.