fallback: legalize: G_FPTOUI_SAT s8,s16

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_FPTOUI_SAT s8,s16
Occurrences:36 in 22 configs, 1 test files
Snippet from:half-convert.ll @fcvt_wu_s_sat_i8 via llvm-extract
Config:-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define zeroext i8 @fcvt_wu_s_sat_i8(half %a) #0 {
start:
  %0 = tail call i8 @llvm.fptoui.sat.i8.f16(half %a)
  ret i8 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i8 @llvm.fptoui.sat.i8.f16(half) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(s8) = G_FPTOUI_SAT %0:_(s16) (in function: fcvt_wu_s_sat_i8)
warning: Instruction selection used fallback path for fcvt_wu_s_sat_i8

Occurrences (36):

InputFunctionConfig
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs -target-abi ilp32d
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv32 -verify-machineinstrs
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs -target-abi lp64d
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-convert.llfcvt_wu_s_sat_i8-mtriple=riscv64 -verify-machineinstrs
half-convert.0dca878d10.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs
half-convert.17eabf72ba.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs -target-abi ilp32
half-convert.1dd77f3397.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs
half-convert.202a98149b.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -verify-machineinstrs
half-convert.24846e311b.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f
half-convert.3bd73a2b15.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs -target-abi ilp32d
half-convert.54de1a81a1.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d
half-convert.68830b883b.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32
half-convert.7573dd816f.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs -target-abi lp64
half-convert.79c58dcddb.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi ilp32
half-convert.812a559d3b.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-convert.81b058419d.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-convert.897671e4df.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zdinx,+zhinxmin -verify-machineinstrs -target-abi lp64
half-convert.a98a79b5cb.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs
half-convert.af01676ebd.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -verify-machineinstrs
half-convert.b48ed180ae.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs
half-convert.c41958b326.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64
half-convert.ccf3b5add6.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f
half-convert.da2cfbf4b2.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+zdinx,+zhinxmin -verify-machineinstrs -target-abi ilp32
half-convert.dab903f165.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64
half-convert.db94af7466.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs -target-abi lp64d
half-convert.e9a571ea93.ll (mutant of half-convert.ll)fcvt_wu_s_sat_i8-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d

Generated 2026-10-15 08:05 UTC.