fallback: legalize: G_FSUB s16

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_FSUB s16
Occurrences:67 in 29 configs, 9 test files
Snippet from:half-arith.ll @fsub_h via llvm-extract
Config:-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define half @fsub_h(half %a, half %b) #0 {
  %1 = fsub half %a, %b
  ret half %1
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(s16) = G_FSUB %0:_, %1:_ (in function: fsub_h)
warning: Instruction selection used fallback path for fsub_h

Occurrences (67) (first 50):

InputFunctionConfig
half-arith.llfsub_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfmsub_h_contract-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfnmadd_h_contract-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfnmsub_h_contract-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfsub_h-mtriple=riscv32 -verify-machineinstrs
half-arith.llfmsub_h_contract-mtriple=riscv32 -verify-machineinstrs
half-arith.llfnmadd_h_contract-mtriple=riscv32 -verify-machineinstrs
half-arith.llfnmsub_h_contract-mtriple=riscv32 -verify-machineinstrs
half-arith.llfsub_h-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfmsub_h_contract-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfnmadd_h_contract-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfnmsub_h_contract-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfsub_h-mtriple=riscv64 -verify-machineinstrs
half-arith.llfmsub_h_contract-mtriple=riscv64 -verify-machineinstrs
half-arith.llfnmadd_h_contract-mtriple=riscv64 -verify-machineinstrs
half-arith.llfnmsub_h_contract-mtriple=riscv64 -verify-machineinstrs
double-intrinsics.133673c6eb.ll (mutant of double-intrinsics.ll)atan_f64-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-intrinsics.25e5d0271e.ll (mutant of double-intrinsics.ll)atan_f64-mtriple=riscv32 -verify-machineinstrs
double-intrinsics.2647543c20.ll (mutant of double-intrinsics.ll)atan_f64-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-intrinsics.68b93253b8.ll (mutant of double-intrinsics.ll)atan_f64-mtriple=riscv64 -verify-machineinstrs
double-intrinsics.e24fa10599.ll (mutant of double-intrinsics.ll)atan_f64-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-intrinsics.fb2d2a6a8d.ll (mutant of double-intrinsics.ll)atan_f64-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
half-arith.04514350e7.ll (mutant of half-arith.ll)fnmadd_h_contract-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.05c8eb1503.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi ilp32
half-arith.27df414b8c.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64
half-arith.2b2df97445.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv64 -verify-machineinstrs
half-arith.2d863d37b6.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64
half-arith.688da0ee3a.ll (mutant of half-arith.ll)fnmadd_h_contract-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.704b4317db.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv32 -verify-machineinstrs
half-arith.cb7d37ed23.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32
half-arith.cfce1ffcac.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.ebfb0ca3a8.ll (mutant of half-arith.ll)fnmadd_h_contract-mtriple=riscv64 -verify-machineinstrs
half-arith.f051d3022e.ll (mutant of half-arith.ll)fnmadd_h_contract-mtriple=riscv32 -verify-machineinstrs
half-arith.fb38d3d3bc.ll (mutant of half-arith.ll)fsub_h-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-convert.04a242509c.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-convert.0b053bddb9.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs
half-convert.2f90c56a63.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d
half-convert.40b6cb13e8.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv64 -verify-machineinstrs
half-convert.4aa8ea8be2.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d
half-convert.6993091859.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs
half-convert.6c7fd55a4d.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv32 -verify-machineinstrs
half-convert.7883c190c1.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs
half-convert.afd03fc7d0.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-convert.d4645b0270.ll (mutant of half-convert.ll)fcvt_l_h-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs
half-maximum-minimum.4acb789474.ll (mutant of half-maximum-minimum.ll)fmaximum_nnan_op_f16-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi ilp32
half-maximum-minimum.4f56508461.ll (mutant of half-maximum-minimum.ll)fminimum_nnan_attr_f16-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64
half-maximum-minimum.53e30926b7.ll (mutant of half-maximum-minimum.ll)fmaximum_nnan_op_f16-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-maximum-minimum.5614f024a6.ll (mutant of half-maximum-minimum.ll)fminimum_nnan_attr_f16-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-maximum-minimum.7d9876aea2.ll (mutant of half-maximum-minimum.ll)fmaximum_nnan_op_f16-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64
half-maximum-minimum.c2cf1fce4d.ll (mutant of half-maximum-minimum.ll)fminimum_nnan_attr_f16-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f

Generated 2026-10-15 08:05 UTC.