fallback: legalize: G_INSERT_SUBVECTOR <vscale x 2 x s32>,<4 x s32>

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_INSERT_SUBVECTOR <vscale x 2 x s32>,<4 x s32>
Occurrences:39 in 7 configs, 3 test files
Snippet from:nontemporal.ll @test_nontemporal_load_v4i32 via llvm-extract
Config:-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <4 x i32> @test_nontemporal_load_v4i32(ptr %p) {
  %1 = load <4 x i32>, ptr %p, align 16, !nontemporal !0
  ret <4 x i32> %1
}

!0 = !{i32 1}

Reproduce:

llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %3:_(<vscale x 2 x s32>) = G_INSERT_SUBVECTOR %2:_, %1:_(<4 x s32>), 0 (in function: test_nontemporal_load_v4i32)
warning: Instruction selection used fallback path for test_nontemporal_load_v4i32

Occurrences (39):

InputFunctionConfig
nontemporal.lltest_nontemporal_load_v4i32-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_P1_load_v4i32-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_PALL_load_v4i32-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_S1_load_v4i32-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_ALL_load_v4i32-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_load_v4i32-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_P1_load_v4i32-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_PALL_load_v4i32-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_S1_load_v4i32-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.lltest_nontemporal_ALL_load_v4i32-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
usub_sat.llfun12-mtriple=riscv32 -mattr=+m,+v
usub_sat.llfun13-mtriple=riscv32 -mattr=+m,+v
usub_sat.llfun14-mtriple=riscv32 -mattr=+m,+v
usub_sat.llfun12-mtriple=riscv32 -mattr=+m,+zbb,+v
usub_sat.llfun13-mtriple=riscv32 -mattr=+m,+zbb,+v
usub_sat.llfun14-mtriple=riscv32 -mattr=+m,+zbb,+v
usub_sat.llfun12-mtriple=riscv64 -mattr=+m,+v
usub_sat.llfun13-mtriple=riscv64 -mattr=+m,+v
usub_sat.llfun14-mtriple=riscv64 -mattr=+m,+v
usub_sat.llfun12-mtriple=riscv64 -mattr=+m,+zbb,+v
usub_sat.llfun13-mtriple=riscv64 -mattr=+m,+zbb,+v
usub_sat.llfun14-mtriple=riscv64 -mattr=+m,+zbb,+v
zero-call-used-regs-v.llused_arg-verify-machineinstrs -mtriple=riscv64 -mattr=+v
zero-call-used-regs-v.llused_arg_fixed_x10-verify-machineinstrs -mtriple=riscv64 -mattr=+v
nontemporal.2322e66266.ll (mutant of nontemporal.ll)test_nontemporal_S1_load_v4i32-mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v
nontemporal.4ba7e78c91.ll (mutant of nontemporal.ll)test_nontemporal_S1_load_v4i32-mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v
usub_sat.1e1fd43476.ll (mutant of usub_sat.ll)fun12-mtriple=riscv32 -mattr=+m,+zbb,+v
usub_sat.2f546e960b.ll (mutant of usub_sat.ll)fun13-mtriple=riscv32 -mattr=+m,+zbb,+v
usub_sat.36d4ffa9dc.ll (mutant of usub_sat.ll)fun12-mtriple=riscv32 -mattr=+m,+v
usub_sat.40dde907fc.ll (mutant of usub_sat.ll)fun12-mtriple=riscv32 -mattr=+m,+v
usub_sat.611eac3973.ll (mutant of usub_sat.ll)fun12-mtriple=riscv64 -mattr=+m,+v
usub_sat.75d61a756a.ll (mutant of usub_sat.ll)fun12-mtriple=riscv64 -mattr=+m,+zbb,+v
usub_sat.901b0a1e47.ll (mutant of usub_sat.ll)fun13-mtriple=riscv64 -mattr=+m,+zbb,+v
usub_sat.917de26e6f.ll (mutant of usub_sat.ll)fun12-mtriple=riscv64 -mattr=+m,+zbb,+v
usub_sat.9304fcb7a3.ll (mutant of usub_sat.ll)fun13-mtriple=riscv64 -mattr=+m,+v
usub_sat.9b9b1caf4c.ll (mutant of usub_sat.ll)fun13-mtriple=riscv32 -mattr=+m,+v
usub_sat.b801bde7f6.ll (mutant of usub_sat.ll)fun12-mtriple=riscv32 -mattr=+m,+zbb,+v
usub_sat.f2b6498cf2.ll (mutant of usub_sat.ll)fun12-mtriple=riscv64 -mattr=+m,+v
zero-call-used-regs-v.a1d9579463.ll (mutant of zero-call-used-regs-v.ll)used_arg_fixed_x10-verify-machineinstrs -mtriple=riscv64 -mattr=+v

Generated 2026-10-15 08:05 UTC.