fallback: legalize: G_OR <4 x s16>

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_OR <4 x s16>
Occurrences:9 in 6 configs, 3 test files
Snippet from:rvp-simd-64.ll @test_or_h via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <4 x i16> @test_or_h(<4 x i16> %a, <4 x i16> %b) {
  %res = or <4 x i16> %a, %b
  ret <4 x i16> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<4 x s16>) = G_OR %0:_, %1:_ (in function: test_or_h)
warning: Instruction selection used fallback path for test_or_h

Occurrences (9):

InputFunctionConfig
rvp-bitreverse-zbkb.lltest_bitreverse_v4i16-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb,+zbkb -verify-machineinstrs
rvp-simd-64.lltest_or_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_orn_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_bitreverse_v4i16-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-bitreverse-zbkb.08f22c9e32.ll (mutant of rvp-bitreverse-zbkb.ll)test_bitreverse_v4i16-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb,+zbkb -verify-machineinstrs
rvp-unaligned-load-store.28a79b422b.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i16_align4-mtriple=riscv64 -mattr=+experimental-p
rvp-unaligned-load-store.4e581e9ac9.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i16_align4-mtriple=riscv32 -mattr=+experimental-p
rvp-unaligned-load-store.a55cbec258.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i16_align4-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem
rvp-unaligned-load-store.ce61079946.ll (mutant of rvp-unaligned-load-store.ll)test_load_v4i16_align4-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem

Generated 2026-10-15 08:05 UTC.