fallback: legalize: G_SDIV <8 x s8>

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_SDIV <8 x s8>
Occurrences:55 in 43 configs, 17 test files
Snippet from:rvp-simd-64.ll @test_psdiv_b via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <8 x i8> @test_psdiv_b(<8 x i8> %a, <8 x i8> %b) {
  %res = sdiv <8 x i8> %a, %b
  ret <8 x i8> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<8 x s8>) = G_SDIV %0:_, %1:_ (in function: test_psdiv_b)
warning: Instruction selection used fallback path for test_psdiv_b

Occurrences (55) (first 50):

InputFunctionConfig
rvp-simd-64.lltest_psdiv_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_psdiv_mulhs_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_psdiv_mulhsu_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
add_sext_shl_constant.482851f005.ll (mutant of add_sext_shl_constant.ll)add_shl_sext-mtriple=riscv64
add_sext_shl_constant.772f449726.ll (mutant of add_sext_shl_constant.ll)add_shl_sext-mtriple=riscv64 -mattr=+xandesperf
add_sext_shl_constant.82784a8144.ll (mutant of add_sext_shl_constant.ll)add_shl_sext-mtriple=riscv64 -mattr=+zba
bswap-known-bits.2b5f86f5e8.ll (mutant of bswap-known-bits.ll)bswap_src_zext_i16_to_i64-mtriple=riscv32 -mattr=+zbb -verify-machineinstrs
bswap-known-bits.9eed7fa4af.ll (mutant of bswap-known-bits.ll)bswap_src_zext_i16_to_i64-mtriple=riscv64 -mattr=+zbb -verify-machineinstrs
bswap-shift.1e42eb3abd.ll (mutant of bswap-shift.ll)test_bswap_shli_16_bswap_i32-mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs
bswap-shift.a992b23d04.ll (mutant of bswap-shift.ll)test_bswap_shli_16_bswap_i32-mtriple=riscv32 -mattr=+zbb -verify-machineinstrs
bswap-shift.c93e40fd17.ll (mutant of bswap-shift.ll)test_bswap_shli_16_bswap_i32-mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs
bswap-shift.c95ebc0020.ll (mutant of bswap-shift.ll)test_bswap_shli_16_bswap_i32-mtriple=riscv64 -mattr=+zbb -verify-machineinstrs
calling-conv-ilp32d.28dfea5ed4.ll (mutant of calling-conv-ilp32d.ll)caller_double_on_stack_exhausted_gprs_fprs-mtriple=riscv32 -verify-machineinstrs -mattr=+d -target-abi ilp32d
calls.2d5f2b2c27.ll (mutant of calls.ll)defined_many_args-code-model=large -mtriple=riscv64 -verify-machineinstrs
calls.4baf55e2d8.ll (mutant of calls.ll)defined_many_args-code-model=large -mtriple=riscv64 -mattr=experimental-zicfilp -verify-machineinstrs
calls.5d03051ec5.ll (mutant of calls.ll)defined_many_args-relocation-model=pic -mtriple=riscv32 -verify-machineinstrs
calls.89e691d19c.ll (mutant of calls.ll)defined_many_args-code-model=medium -mtriple=riscv64 -verify-machineinstrs
calls.951c63ba1c.ll (mutant of calls.ll)defined_many_args-mtriple=riscv32 -verify-machineinstrs
calls.cac0552561.ll (mutant of calls.ll)defined_many_args-mtriple=riscv64 -verify-machineinstrs
calls.e25fe411ed.ll (mutant of calls.ll)defined_many_args-code-model=small -mtriple=riscv64 -verify-machineinstrs
cmov-branch-opt.042e2d6176.ll (mutant of cmov-branch-opt.ll)select_or_b-mtriple=riscv64 -mattr=+c -verify-machineinstrs
cmov-branch-opt.25a7cb3bf6.ll (mutant of cmov-branch-opt.ll)select_or_b-mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+zicond -verify-machineinstrs
cmov-branch-opt.331010b9c2.ll (mutant of cmov-branch-opt.ll)select_or_b-mtriple=riscv64 -mattr=+short-forward-branch-ialu,+c -verify-machineinstrs
cmov-branch-opt.62aaf9a1b3.ll (mutant of cmov-branch-opt.ll)select_or_b-mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c -verify-machineinstrs
cmov-branch-opt.83df676450.ll (mutant of cmov-branch-opt.ll)select_or_b-mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs
cmov-branch-opt.ebda4db768.ll (mutant of cmov-branch-opt.ll)select_or_b-mtriple=riscv64 -mattr=+short-forward-branch-ialu,+zicond -verify-machineinstrs
cmov-branch-opt.f884fb623f.ll (mutant of cmov-branch-opt.ll)select_or_b-mtriple=riscv64 -mattr=+short-forward-branch-ialu -verify-machineinstrs
double-select-icmp.1cb7bf8bd9.ll (mutant of double-select-icmp.ll)select_icmp_sle-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-select-icmp.c78df76642.ll (mutant of double-select-icmp.ll)select_icmp_sle-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-select-icmp.e14c793dc9.ll (mutant of double-select-icmp.ll)select_icmp_sle-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-select-icmp.e53e9a925b.ll (mutant of double-select-icmp.ll)select_icmp_sle-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
float-select-icmp.324378d490.ll (mutant of float-select-icmp.ll)select_icmp_sle-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-select-icmp.edb9d9af0c.ll (mutant of float-select-icmp.ll)select_icmp_sle-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
fold-masked-merge.212eeb9bea.ll (mutant of fold-masked-merge.ll)masked_merge_no_transform0-mtriple=riscv64
fold-masked-merge.51b8b09c6c.ll (mutant of fold-masked-merge.ll)masked_merge_no_transform0-mtriple=riscv32
fold-masked-merge.826ec0b18f.ll (mutant of fold-masked-merge.ll)masked_merge_no_transform0-mtriple=riscv32 -mattr=+zbb
fold-masked-merge.ee6a55f982.ll (mutant of fold-masked-merge.ll)masked_merge_no_transform0-mtriple=riscv64 -mattr=+zbb
half-select-icmp.0283e931b4.ll (mutant of half-select-icmp.ll)select_icmp_sle-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi=lp64f
half-select-icmp.0d26935772.ll (mutant of half-select-icmp.ll)select_icmp_sle-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f
half-select-icmp.3026915d3c.ll (mutant of half-select-icmp.ll)select_icmp_sle-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f
half-select-icmp.9ede773ffa.ll (mutant of half-select-icmp.ll)select_icmp_sle-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f
machine-sink-load-immediate.e0958a18ab.ll (mutant of machine-sink-load-immediate.ll)switch_dispatch-mtriple=riscv64
rv64d-double-convert.2c6a257222.ll (mutant of rv64d-double-convert.ll)sitofp_aext_i32_to_f64-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
rv64d-double-convert.e70a2f9ff5.ll (mutant of rv64d-double-convert.ll)sitofp_aext_i32_to_f64-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
shift-masked-shamt.cccded05b6.ll (mutant of shift-masked-shamt.ll)sll_redundant_mask_zeros_i64-mtriple=riscv64 -verify-machineinstrs
shift-masked-shamt.fadd513eef.ll (mutant of shift-masked-shamt.ll)sll_redundant_mask_zeros_i64-mtriple=riscv32 -verify-machineinstrs
short-forward-branch-opt-zibi.198d43e0a0.ll (mutant of short-forward-branch-opt-zibi.ll)select_eq_minsize-mtriple=riscv32 -mattr=+experimental-zibi,+short-forward-branch-ialu -verify-machineinstrs
short-forward-branch-opt-zibi.7361780a24.ll (mutant of short-forward-branch-opt-zibi.ll)select_eq_minsize-mtriple=riscv32 -mattr=+experimental-zibi -verify-machineinstrs
short-forward-branch-opt-zibi.7b26beecf4.ll (mutant of short-forward-branch-opt-zibi.ll)select_eq_minsize-mtriple=riscv32 -mattr=+experimental-zibi,+zca,+conditional-cmv-fusion -verify-machineinstrs
short-forward-branch-opt-zibi.96d05b19dc.ll (mutant of short-forward-branch-opt-zibi.ll)select_eq_minsize-mtriple=riscv64 -mattr=+experimental-zibi,+short-forward-branch-ialu -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.