fallback: legalize: G_VECREDUCE_ADD s16,<16 x s16>

Run:explore-04ca53e65f-20261014-114124
Kind:fallback
Category:legalize: G_VECREDUCE_ADD s16,<16 x s16>
Occurrences:4 in 2 configs, 1 test files
Snippet from:double_reduct.ll @add_ext_i16 via llvm-extract
Config:-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {
  %ae = zext <16 x i8> %a to <16 x i16>
  %be = zext <16 x i8> %b to <16 x i16>
  %r1 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %ae)
  %r2 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %be)
  %r = add i16 %r1, %r2
  ret i16 %r
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>) #0

attributes #0 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %7:_(s16) = G_VECREDUCE_ADD %5:_(<16 x s16>) (in function: add_ext_i16)
warning: Instruction selection used fallback path for add_ext_i16

Occurrences (4):

InputFunctionConfig
double_reduct.lladd_ext_i16-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs
double_reduct.lladd_ext_v32i16-mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs
double_reduct.lladd_ext_i16-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs
double_reduct.lladd_ext_v32i16-mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.