regression: +77 insts: add_shl_moreOneUse_inStore (add_shl_constant.ll)

Snippet:

@G = external global i128

define void @add_shl_moreOneUse_inStore(ptr %array1, i32 %a, i32 %b) {
entry:
  %LGV = load i128, ptr @G, align 4
  %add = add nsw i32 %a, 5
  %arrayidx = getelementptr inbounds i32, ptr %array1, i32 %add
  store i32 %b, ptr %arrayidx, align 4
  %B = ashr i128 -1, %LGV
  %0 = getelementptr i32, ptr %array1, i32 %a
  %arrayidx3 = getelementptr i8, ptr %0, i32 24
  store i32 %b, ptr %arrayidx3, align 4
  %arrayidx5 = getelementptr i8, ptr %0, i32 140
  store i32 %add, ptr %arrayidx5, align 4
  store i128 %B, ptr %arrayidx5, align 4
  ret void
}

Reproduce:

llc -mtriple=riscv32 -global-isel snippet.ll -o -
llc -mtriple=riscv32 -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,10 +1,105 @@
+lui a3, %hi(G)
+lw a4, %lo(G)(a3)
+addi a3, a1, 5
+slli a5, a3, 2
+add a6, a0, a5
+li a5, -1
+sw a2, 0(a6)
+li t2, 32
+neg t5, a4
+srl t0, a5, a4
+sll t1, a5, t5
+bltu a4, t2, .L0
+sra a7, a5, a4
+li a6, -1
+bnez a4, .L1
+j .L2
+.L0:
+or a7, t0, t1
+li a6, -1
+beqz a4, .L2
+.L1:
+mv a6, a7
+.L2:
+srl t6, a5, a4
+bltu a4, t2, .L3
+srai a7, a5, 31
+j .L4
+.L3:
+sra a7, a5, a4
+or t6, t6, t1
+.L4:
+li t3, 64
+li t4, -1
+beqz a4, .L5
+mv t4, t6
+.L5:
+sub t6, t3, a4
+bltu a4, t2, .L6
+li t0, 0
+.L6:
+addi sp, sp, -16
+sw s0, 12(sp)
+sw s1, 8(sp)
+bltu t6, t2, .L7
+li t1, 0
+sll s1, a5, t6
+j .L8
+.L7:
+neg s0, t6
+srl s0, a5, s0
+sll s1, a5, t5
+or s1, s0, s1
+.L8:
+addi s0, a4, -64
+li t5, -1
+beqz t6, .L9
+mv t5, s1
+.L9:
+bltu s0, t2, .L10
+sra s1, a5, s0
+li t6, -1
+bnez s0, .L11
+j .L12
+.L10:
+neg t6, s0
+srl s1, a5, a4
+sll t6, a5, t6
+or s1, s1, t6
+li t6, -1
+beqz s0, .L12
+.L11:
+mv t6, s1
+.L12:
+bltu s0, t2, .L13
+srai t2, a5, 31
+j .L14
+.L13:
+sra t2, a5, a4
+.L14:
+lw s0, 12(sp)
+lw s1, 8(sp)
+addi sp, sp, 16
+bgeu a4, t3, .L15
+or t6, t4, t1
+or t2, t0, t5
+.L15:
+li t1, -1
+li t0, -1
+beqz a4, .L16
+mv t1, t6
+mv t0, t2
+.L16:
+bltu a4, t3, .L17
+srai a6, a5, 31
+mv a7, a6
+.L17:
 slli a1, a1, 2
 add a0, a0, a1
-li a1, -1
-sw a2, 20(a0)
 sw a2, 24(a0)
-sw a1, 140(a0)
-sw a1, 144(a0)
-sw a1, 148(a0)
-sw a1, 152(a0)
+sw a3, 140(a0)
+sw t1, 140(a0)
+sw a6, 148(a0)
+sw t0, 144(a0)
+sw a7, 152(a0)
 ret

Occurrences (1):

Generated 2026-10-15 08:05 UTC.