regression: +62 insts: foo (select-cc.ll)

Snippet:

@G = external global double
@G.1 = external global i1

; Function Attrs: nounwind
define signext i32 @foo(i32 signext %a, ptr %b) #0 {
  %LGV = load double, ptr @G, align 8
  %val1 = load volatile i32, ptr %b, align 4
  %tst1 = icmp eq i32 %a, %val1
  %val2 = select i1 %tst1, i32 %a, i32 %val1
  %val3 = load volatile i32, ptr %b, align 4
  %tst2 = icmp ne i32 %val2, %val3
  %val4 = select i1 %tst2, i32 %val2, i32 %val3
  %val5 = load volatile i32, ptr %b, align 4
  %tst3 = icmp ugt i32 %val4, %val5
  %val6 = select i1 %tst3, i32 %val4, i32 %val5
  %val7 = load volatile i32, ptr %b, align 4
  %tst4 = icmp uge i32 %val6, %val7
  %val8 = select i1 %tst4, i32 %val6, i32 %val7
  %val9 = load volatile i32, ptr %b, align 4
  %tst5 = icmp ult i32 %val8, %val9
  %val10 = select i1 %tst5, i32 %val8, i32 %val9
  %val11 = load volatile i32, ptr %b, align 4
  %tst6 = icmp ule i32 %val10, %val11
  %val12 = select i1 %tst6, i32 %val10, i32 %val11
  %val13 = load volatile i32, ptr %b, align 4
  %tst7 = icmp sgt i32 %val12, %val13
  %val14 = select i1 %tst7, i32 %val12, i32 %val13
  %val15 = load volatile i32, ptr %b, align 4
  %tst8 = icmp sge i32 %val14, %val15
  %val16 = select i1 %tst8, i32 %val14, i32 %val15
  %val17 = load volatile i32, ptr %b, align 4
  %tst9 = icmp slt i32 %val16, %val17
  %val18 = select i1 %tst9, i32 %val16, i32 %val17
  %val19 = load volatile i32, ptr %b, align 4
  %tst10 = icmp sle i32 %val18, %val19
  %val20 = select i1 %tst10, i32 %val18, i32 %val19
  %val21 = load volatile i32, ptr %b, align 4
  %tst11 = icmp slt i32 %val21, 1
  %val22 = select i1 %tst11, i32 %val20, i32 %val21
  %val23 = load volatile i32, ptr %b, align 4
  %tst12 = icmp sgt i32 %val21, -1
  %val24 = select i1 %tst12, i32 %val22, i32 %val23
  %val25 = load volatile i32, ptr %b, align 4
  %C = fcmp olt double +qnan, %LGV
  %tst13 = icmp sgt i32 %val25, 1024
  %val26 = select i1 %tst13, i32 %val24, i32 %val25
  %val27 = load volatile i32, ptr %b, align 4
  %tst14 = icmp ugt i32 %val21, 2046
  %val28 = select i1 %tst14, i32 %val26, i32 %val27
  store i1 %C, ptr @G.1, align 1
  ret i32 %val28
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,35 +1,118 @@
-lw a2, 0(a1)
-lw a3, 0(a1)
+addi sp, sp, -32
+sw ra, 28(sp)
+sw s0, 24(sp)
+sw s1, 20(sp)
+sw s2, 16(sp)
+sw s3, 12(sp)
+sw s4, 8(sp)
+sw s5, 4(sp)
+sw s6, 0(sp)
+mv s0, a1
+lui a1, %hi(G)
+addi a1, a1, %lo(G)
 lw a4, 0(a1)
-lw a5, 0(a1)
-lw a6, 0(a1)
-lw a7, 0(a1)
-lw t0, 0(a1)
-lw t1, 0(a1)
-qc.mvne a0, a0, a2, a2
-qc.mveq a0, a0, a3, a3
-qc.mvgeu a0, a4, a0, a4
-qc.mvltu a0, a0, a5, a5
-qc.mvgeu a0, a0, a6, a6
-lw a2, 0(a1)
-qc.mvltu a0, a7, a0, a7
-lw a3, 0(a1)
-qc.mvge a0, t0, a0, t0
-lw a4, 0(a1)
-qc.mvlt a0, a0, t1, t1
-lw a5, 0(a1)
-qc.mvge a0, a0, a2, a2
-lw a2, 0(a1)
-qc.mvlt a0, a3, a0, a3
-lw a1, 0(a1)
-blez a4, .L0
+lw a1, 4(a1)
+lw a2, 0(s0)
+mv s1, a0
+bne a0, a2, .L0
+lw a0, 0(s0)
+beq s1, a0, .L1
+.L2:
+lw a0, 0(s0)
+bgeu a0, s1, .L3
+.L4:
+lw a0, 0(s0)
+bgeu a0, s1, .L5
+.L6:
+lw a0, 0(s0)
+bgeu s1, a0, .L7
+.L8:
+lw a0, 0(s0)
+bgeu s1, a0, .L9
+.L10:
+lw a0, 0(s0)
+bge a0, s1, .L11
+.L12:
+lw a0, 0(s0)
+bge a0, s1, .L13
+.L14:
+lw a0, 0(s0)
+blt s1, a0, .L15
+.L16:
+mv s1, a0
+.L15:
+lw a2, 0(s0)
+lui a0, %hi(.L17)
+blt s1, a2, .L18
+mv s1, a2
+.L18:
+lw s2, 0(s0)
+addi a0, a0, %lo(.L17)
+blez s2, .L19
+mv s1, s2
+.L19:
+lw a2, 0(a0)
+lw a3, 4(a0)
+lw a0, 0(s0)
+li s4, 1024
+bgez s2, .L20
+mv s1, a0
+.L20:
+lw s6, 0(s0)
+lui s3, %hi(G.1)
+li s5, 2046
 mv a0, a4
+call __gtdf2
+blt s4, s6, .L21
+mv s1, s6
+.L21:
+lw a2, 0(s0)
+sgtz a1, a0
+bltu s5, s2, .L22
+mv s1, a2
+.L22:
+mv a0, s1
+sb a1, %lo(G.1)(s3)
+lw ra, 28(sp)
+lw s0, 24(sp)
+lw s1, 20(sp)
+lw s2, 16(sp)
+lw s3, 12(sp)
+lw s4, 8(sp)
+lw s5, 4(sp)
+lw s6, 0(sp)
+addi sp, sp, 32
+ret
 .L0:
-qc.mvlti a0, a4, 0, a5
-li a3, 1024
-qc.mvge a0, a3, a2, a2
-li a2, 2046
-qc.mvgeu a0, a2, a4, a1
-lui a1, %hi(G.1)
-sb zero, %lo(G.1)(a1)
-ret
+mv s1, a2
+lw a0, 0(s0)
+bne a2, a0, .L2
+.L1:
+mv s1, a0
+lw a0, 0(s0)
+bltu a0, s1, .L4
+.L3:
+mv s1, a0
+lw a0, 0(s0)
+bltu a0, s1, .L6
+.L5:
+mv s1, a0
+lw a0, 0(s0)
+bltu s1, a0, .L8
+.L7:
+mv s1, a0
+lw a0, 0(s0)
+bltu s1, a0, .L10
+.L9:
+mv s1, a0
+lw a0, 0(s0)
+blt a0, s1, .L12
+.L11:
+mv s1, a0
+lw a0, 0(s0)
+blt a0, s1, .L14
+.L13:
+mv s1, a0
+lw a0, 0(s0)
+bge s1, a0, .L16
+j .L15

Occurrences (1):

Generated 2026-10-15 08:05 UTC.