regression: +107 insts: fshr128_minsize (shifts.ll)

Snippet:

; Function Attrs: minsize nounwind
define i128 @fshr128_minsize(i128 %a, i128 %b) #0 {
  %res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %b)
  ret i128 %res
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i128 @llvm.fshr.i128(i128, i128, i128) #1

attributes #0 = { minsize nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,59 +1,193 @@
-lw a2, 0(a2)
-lw t1, 0(a1)
-lw a7, 4(a1)
-lw a4, 8(a1)
-lw a1, 12(a1)
-andi t2, a2, 64
-mv t0, a7
-mv a3, t1
-beqz t2, .L0
-mv t0, a1
-mv a3, a4
+lw t3, 0(a2)
+lw a2, 12(a1)
+lw a3, 8(a1)
+andi t4, t3, 127
+li a6, 32
+neg t6, t4
+sll t5, a2, t6
+bltu t4, a6, .L0
+srl a5, a2, t4
+j .L1
 .L0:
-andi a6, a2, 32
-mv a5, a3
-bnez a6, .L1
-bnez t2, .L2
+srl a4, a3, t3
+or a5, a4, t5
+.L1:
+mv a4, a3
+beqz t4, .L2
+mv a4, a5
+.L2:
+lw a7, 0(a1)
+lw a5, 4(a1)
+bltu t4, a6, .L3
+li a1, 0
+srl t2, a5, t4
+j .L4
 .L3:
-beqz a6, .L4
+srl t0, a7, t3
+sll t1, a5, t6
+srl a1, a2, t3
+or t2, t0, t1
+.L4:
+li t0, 64
+mv t1, a7
+beqz t4, .L5
+mv t1, t2
 .L5:
-mv t0, a4
-.L4:
-slli t3, t0, 1
-not t1, a2
-beqz t2, .L6
-mv a1, a7
+addi sp, sp, -32
+sw s0, 28(sp)
+sw s1, 24(sp)
+sw s2, 20(sp)
+sw s3, 16(sp)
+sw s4, 12(sp)
+sw s5, 8(sp)
+sub s0, t0, t4
+bltu t4, a6, .L6
+li t2, 0
+bgeu s0, a6, .L7
+.L8:
+neg s1, s0
+srl s1, a3, s1
+sll t6, a3, t6
+or s2, s1, t5
+j .L9
 .L6:
-srl a7, a5, a2
-sll t2, t3, t1
-srl t0, t0, a2
-beqz a6, .L7
-mv a4, a1
+srl t2, a5, t3
+bltu s0, a6, .L8
 .L7:
-slli t3, a4, 1
-or a7, t2, a7
-sll t2, t3, t1
-or t0, t2, t0
-srl a4, a4, a2
-beqz a6, .L8
-mv a1, a3
-.L8:
-slli a3, a1, 1
-srl a1, a1, a2
-slli a5, a5, 1
-sll a2, a3, t1
-sll a3, a5, t1
-or a2, a2, a4
-or a1, a3, a1
-sw a7, 0(a0)
-sw t0, 4(a0)
-sw a2, 8(a0)
+li t6, 0
+sll s2, a3, s0
+.L9:
+addi s1, t4, -64
+mv t5, a2
+beqz s0, .L10
+mv t5, s2
+.L10:
+bltu s1, a6, .L11
+srl s2, a2, s1
+j .L12
+.L11:
+neg s0, s1
+srl s2, a3, t4
+sll s0, a2, s0
+or s2, s2, s0
+.L12:
+mv s0, a3
+beqz s1, .L13
+mv s0, s2
+.L13:
+bltu s1, a6, .L14
+li s1, 0
+bltu t4, t0, .L15
+j .L16
+.L14:
+srl s1, a2, t4
+bgeu t4, t0, .L16
+.L15:
+or s0, t1, t6
+or s1, t2, t5
+.L16:
+mv t1, a7
+mv t2, a5
+beqz t4, .L17
+mv t1, s0
+mv t2, s1
+.L17:
+neg t6, t3
+bltu t4, t0, .L18
+li a4, 0
+li a1, 0
+.L18:
+andi t3, t6, 127
+neg s2, t3
+srl s0, a7, s2
+bltu t3, a6, .L19
+li t4, 0
+sll s3, a7, t3
+j .L20
+.L19:
+sll t5, a5, t6
+sll t4, a7, t6
+or s3, s0, t5
+.L20:
+sub s1, t0, t3
+mv t5, a5
+beqz t3, .L21
+mv t5, s3
+.L21:
+bltu s1, a6, .L22
+srl s3, a5, s1
+j .L23
+.L22:
+neg s3, s1
+sll s3, a5, s3
+or s3, s0, s3
+.L23:
+mv s0, a7
+beqz s1, .L24
+mv s0, s3
+.L24:
+bltu s1, a6, .L25
+li s1, 0
+bgeu t3, a6, .L26
+.L27:
+srl s2, a3, s2
+sll s3, a2, t6
+sll t6, a3, t6
+or s4, s2, s3
+j .L28
+.L25:
+srl s1, a5, s2
+bltu t3, a6, .L27
+.L26:
+li t6, 0
+sll s4, a3, t3
+.L28:
+addi s3, t3, -64
+mv s2, a2
+beqz t3, .L29
+mv s2, s4
+.L29:
+bltu s3, a6, .L30
+li a6, 0
+sll a7, a7, s3
+bnez s3, .L31
+j .L32
+.L30:
+neg a6, s3
+srl s4, a7, a6
+sll s5, a5, t3
+sll a6, a7, t3
+or a7, s4, s5
+beqz s3, .L32
+.L31:
+mv a5, a7
+.L32:
+bltu t3, t0, .L33
+li t4, 0
+li t5, 0
+bnez t3, .L34
+j .L35
+.L33:
+or a6, s0, t6
+or a5, s1, s2
+beqz t3, .L35
+.L34:
+mv a3, a6
+mv a2, a5
+.L35:
+or a5, t1, t4
+or a6, t2, t5
+or a3, a4, a3
+or a1, a1, a2
+sw a5, 0(a0)
+sw a6, 4(a0)
+sw a3, 8(a0)
 sw a1, 12(a0)
+lw s0, 28(sp)
+lw s1, 24(sp)
+lw s2, 20(sp)
+lw s3, 16(sp)
+lw s4, 12(sp)
+lw s5, 8(sp)
+addi sp, sp, 32
 ret
-.L1:
-mv a5, t0
-beqz t2, .L3
-.L2:
-mv a4, t1
-bnez a6, .L5
-j .L4

Occurrences (1):

Generated 2026-10-15 08:05 UTC.