regression: +53 insts: fsrd (xtheadfmemidx.ll)

Snippet:

@G.1 = external global i128

define void @fsrd(ptr %a, i32 %b, double %c) {
  %LGV = load i128, ptr @G.1, align 4
  %1 = fadd double %c, %c
  %2 = getelementptr double, ptr %a, i32 %b
  %L = load i128, ptr %2, align 4
  %B = ashr i128 %LGV, %L
  store double %1, ptr %2, align 8
  store i128 %B, ptr poison, align 4
  ret void
}

Reproduce:

llc -mtriple=riscv32 -mattr=+d,+xtheadfmemidx -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d,+xtheadfmemidx -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,50 +1,122 @@
-addi sp, sp, -32
+addi sp, sp, -16
 lui a2, %hi(G.1)
-addi a2, a2, %lo(G.1)
+addi a3, a2, %lo(G.1)
 slli a1, a1, 3
+lw a6, 0(a3)
+lw t2, 4(a3)
 add a0, a0, a1
-lw a1, 0(a2)
-lw a3, 4(a2)
-lw a4, 8(a2)
-lw a2, 12(a2)
-lw a5, 0(a0)
-sw a1, 0(sp)
-sw a3, 4(sp)
-sw a4, 8(sp)
-sw a2, 12(sp)
-srli a1, a5, 3
-srai a2, a2, 31
-andi a1, a1, 12
-mv a3, sp
-sw a2, 16(sp)
-sw a2, 20(sp)
-sw a2, 24(sp)
-sw a2, 28(sp)
-add a1, a3, a1
-lw a2, 4(a1)
-lw a3, 0(a1)
-andi a4, a5, 31
-lw a6, 8(a1)
-lw a1, 12(a1)
-xori a4, a4, 31
-slli a7, a2, 1
-srl a3, a3, a5
-sll a7, a7, a4
-fadd.d fa5, fa0, fa0
-or a3, a3, a7
-slli a7, a6, 1
-slli t0, a1, 1
-sll a7, a7, a4
-sll a4, t0, a4
-srl a2, a2, a5
-srl a6, a6, a5
-or a2, a2, a7
-or a4, a6, a4
-sra a1, a1, a5
-fsd fa5, 0(a0)
-sw a1, 0(a0)
-sw a4, 0(a0)
-sw a2, 0(a0)
-sw a3, 0(a0)
-addi sp, sp, 32
+lw a1, 0(a0)
+lw a2, 8(a3)
+lw a3, 12(a3)
+sw a6, 8(sp)
+sw t2, 12(sp)
+li a4, 32
+neg t0, a1
+srl a5, a2, a1
+sll t1, a3, t0
+bltu a1, a4, .L0
+sra t3, a3, a1
+mv a7, a2
+bnez a1, .L1
+j .L2
+.L0:
+or t3, a5, t1
+mv a7, a2
+beqz a1, .L2
+.L1:
+mv a7, t3
+.L2:
+bltu a1, a4, .L3
+srai t3, a3, 31
+j .L4
+.L3:
+sra t3, a3, a1
+.L4:
+fld fa5, 8(sp)
+sw a7, 8(sp)
+sw t3, 12(sp)
+bltu a1, a4, .L5
+srl t3, t2, a1
+li a7, 64
+bnez a1, .L6
+j .L7
+.L5:
+srl a7, a6, a1
+sll t3, t2, t0
+or t3, a7, t3
+li a7, 64
+beqz a1, .L7
+.L6:
+mv a6, t3
+.L7:
+sub t3, a7, a1
+bltu a1, a4, .L8
+li t2, 0
+bgeu t3, a4, .L9
+.L10:
+neg t4, t3
+srl t5, a2, t4
+sll t4, a2, t0
+or t1, t5, t1
+j .L11
+.L8:
+srl t2, t2, a1
+bltu t3, a4, .L10
+.L9:
+li t4, 0
+sll t1, a2, t3
+.L11:
+addi t0, a1, -64
+mv t5, a3
+beqz t3, .L12
+mv t5, t1
+.L12:
+fld fa4, 8(sp)
+or a6, a6, t4
+or t1, t2, t5
+sw a6, 8(sp)
+sw t1, 12(sp)
+fld fa3, 8(sp)
+srai a6, a3, 31
+sw a6, 8(sp)
+sw a6, 12(sp)
+bltu t0, a4, .L13
+sra a5, a3, t0
+bnez t0, .L14
+j .L15
+.L13:
+neg t1, t0
+sll t1, a3, t1
+or a5, a5, t1
+beqz t0, .L15
+.L14:
+mv a2, a5
+.L15:
+bgeu t0, a4, .L16
+sra a6, a3, a1
+.L16:
+fld fa2, 8(sp)
+sw a2, 8(sp)
+sw a6, 12(sp)
+beqz a1, .L17
+fmv.d fa5, fa3
+bltu a1, a7, .L17
+fld fa5, 8(sp)
+.L17:
+fadd.d fa3, fa0, fa0
+bltu a1, a7, .L18
+fmv.d fa4, fa2
+.L18:
+fsd fa3, 0(a0)
+fsd fa5, 8(sp)
+lw a0, 8(sp)
+lw a1, 12(sp)
+fsd fa4, 8(sp)
+lw a2, 8(sp)
+lw a3, 12(sp)
+sw a0, 0(a0)
+sw a1, 4(a0)
+sw a2, 8(a0)
+sw a3, 12(a0)
+addi sp, sp, 16
 ret

Occurrences (1):

Generated 2026-10-15 08:05 UTC.