crash: Assertion failed: ((TypeSize::ScalarTy)SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && "input scalars do not exactly cover the output vector register"), function buildInstr, file MachineIRBuilder.cpp

Snippet:

define <2 x double> @v2f64(<2 x double> %x) {
  ret <2 x double> %x
}

Compiler Explorer panes:

Reproduce:

llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 -global-isel=0 snippet.ll -o -

Local llc output:

llc: /home/runner/work/llvm-fuzz/llvm-fuzz/llvm-project/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:1550: virtual MachineInstrBuilder llvm::MachineIRBuilder::buildInstr(unsigned int, ArrayRef<DstOp>, ArrayRef<SrcOp>, std::optional<unsigned int>): Assertion `(TypeSize::ScalarTy)SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && "input scalars do not exactly cover the output vector register"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0.	Program arguments: /home/runner/work/llvm-fuzz/llvm-fuzz/llvm-project/build/bin/llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* -o -
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'IRTranslator' on function '@v2f64'
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  llc       0x000056153b9c554b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 43
1  llc       0x000056153b9c23f1 llvm::sys::RunSignalHandlers() + 369
2  llc       0x000056153b9c5fcb
3  libc.so.6 0x00007f3c04245330
4  libc.so.6 0x00007f3c0429ec0c pthread_kill + 284
5  libc.so.6 0x00007f3c0424527e gsignal + 30
6  libc.so.6 0x00007f3c042288ff abort + 223
7  libc.so.6 0x00007f3c0422881b
8  libc.so.6 0x00007f3c0423b517
9  llc       0x000056153db27563 llvm::MachineIRBuilder::buildInstr(unsigned int, llvm::ArrayRef<llvm::DstOp>, llvm::ArrayRef<llvm::SrcOp>, std::optional<unsigned int>) + 8995
10 llc       0x000056153da3f003 llvm::CSEMIRBuilder::buildInstr(unsigned int, llvm::ArrayRef<llvm::DstOp>, llvm::ArrayRef<llvm::SrcOp>, std::optional<unsigned int>) + 3091
11 llc       0x000056153db1e008 llvm::MachineIRBuilder::buildMergeLikeInstr(llvm::DstOp const&, llvm::ArrayRef<llvm::Register>) + 360
12 llc       0x000056153cbe3692
13 llc       0x000056153da34d90 llvm::CallLowering::handleAssignments(llvm::CallLowering::ValueHandler&, llvm::SmallVectorImpl<llvm::CallLowering::ArgInfo>&, llvm::CCState&, llvm::SmallVectorImpl<llvm::CCValAssign>&, llvm::MachineIRBuilder&, llvm::ArrayRef<llvm::Register>) const + 928
14 llc       0x000056153cbe06ac
15 llc       0x000056153daa1180 llvm::IRTranslatorImpl::runOnMachineFunction(llvm::MachineFunction&, llvm::function_ref<llvm::GISelCSEInfo* ()>, bool, llvm::function_ref<llvm::AAResults* ()>, llvm::function_ref<llvm::BranchProbabilityInfo* ()>, llvm::function_ref<llvm::AssumptionCache* ()>, llvm::TargetLibraryInfo*, llvm::LibcallLoweringInfo const*, llvm::SSPLayoutInfo*) + 3552
16 llc       0x000056153daa242d llvm::IRTranslatorLegacy::runOnMachineFunction(llvm::MachineFunction&) + 733
17 llc       0x000056153bf8c9ed llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 653
18 llc       0x000056153bd1cd37 llvm::FPPassManager::runOnFunction(llvm::Function&) + 871
19 llc       0x000056153bd25232 llvm::FPPassManager::runOnModule(llvm::Module&) + 50
20 llc       0x000056153bd1dae0 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 2000
21 llc       0x000056153b9ccba8 llcMain + 12056
22 llc       0x000056153b9076af main + 63
23 libc.so.6 0x00007f3c0422a1ca
24 libc.so.6 0x00007f3c0422a28b __libc_start_main + 139
25 llc       0x000056153b9075a5 _start + 37

Occurrences (6):

Generated 2026-10-15 08:05 UTC.