fallback: legalize: G_ASHR <4 x s32>

Run:explore-bc8218b282-20261015-075519
Kind:fallback
Category:legalize: G_ASHR <4 x s32>
Occurrences:75 in 44 configs, 22 test files
Snippet from:rvp-simd-64.ll @test_paadd_h via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <4 x i16> @test_paadd_h(<4 x i16> %a, <4 x i16> %b) {
  %ext.a = sext <4 x i16> %a to <4 x i32>
  %ext.b = sext <4 x i16> %b to <4 x i32>
  %add = add nsw <4 x i32> %ext.a, %ext.b
  %shift = ashr <4 x i32> %add, splat (i32 1)
  %res = trunc <4 x i32> %shift to <4 x i16>
  ret <4 x i16> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %7:_(<4 x s32>) = G_ASHR %4:_, %5:_(<4 x s32>) (in function: test_paadd_h)
warning: Instruction selection used fallback path for test_paadd_h

Occurrences (75) (first 50):

InputFunctionConfig
rvp-simd-64.lltest_paadd_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_pasub_h-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_pmulh_v4i16-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
smulh.llsmulh_v4i16-mtriple=riscv32 -mattr=+m
smulh.llsmulh_v4i16-mtriple=riscv64 -mattr=+m
abds-neg.1a8bd9101c.ll (mutant of abds-neg.ll)abd_ext_i8_i16-mtriple=riscv64
abds-neg.35c60c5e93.ll (mutant of abds-neg.ll)abd_ext_i8_i16-mtriple=riscv32
abds-neg.79d1875cb2.ll (mutant of abds-neg.ll)abd_ext_i8_i16-mtriple=riscv64 -mattr=+zbb
abds-neg.9ac042382f.ll (mutant of abds-neg.ll)abd_ext_i8_i16-mtriple=riscv32 -mattr=+zbb
bigendian-load-store.859859f66a.ll (mutant of bigendian-load-store.ll)load_float-mtriple=riscv64 -verify-machineinstrs
bigendian-load-store.c1e9f9a55e.ll (mutant of bigendian-load-store.ll)load_float-mtriple=riscv32 -verify-machineinstrs
condbinops.9609d93743.ll (mutant of condbinops.ll)shl64-mtriple=riscv32
condbinops.c6adf630bd.ll (mutant of condbinops.ll)shl64-mtriple=riscv32 -mattr=+zicond
condbinops.cdec12ceaf.ll (mutant of condbinops.ll)shl64-mtriple=riscv64 -mattr=+xtheadcondmov
condbinops.fcc9670b71.ll (mutant of condbinops.ll)shl64-mtriple=riscv64
condbinops.fe958b191d.ll (mutant of condbinops.ll)shl64-mtriple=riscv64 -mattr=+zicond
ctz_zero_return_test.11d6b7ff52.ll (mutant of ctz_zero_return_test.ll)ctz5-mtriple=riscv64 -verify-machineinstrs
ctz_zero_return_test.2db349d399.ll (mutant of ctz_zero_return_test.ll)ctz5-mtriple=riscv32 -verify-machineinstrs
ctz_zero_return_test.a7f2252297.ll (mutant of ctz_zero_return_test.ll)ctz5-mtriple=riscv32 -mattr=+zbb -verify-machineinstrs
ctz_zero_return_test.e53d8597e4.ll (mutant of ctz_zero_return_test.ll)ctz5-mtriple=riscv64 -mattr=+zbb -verify-machineinstrs
double-fcmp.06826a28bd.ll (mutant of double-fcmp.ll)fcmp_ueq-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-fcmp.163e6e8b27.ll (mutant of double-fcmp.ll)fcmp_ueq-mtriple=riscv32 -verify-machineinstrs
double-fcmp.1b855aa6fd.ll (mutant of double-fcmp.ll)fcmp_ueq-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-fcmp.42e86f7acc.ll (mutant of double-fcmp.ll)fcmp_ueq-mtriple=riscv64 -verify-machineinstrs
double-fcmp.8341146474.ll (mutant of double-fcmp.ll)fcmp_ueq-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-fcmp.d0b7505103.ll (mutant of double-fcmp.ll)fcmp_ueq-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
float-fcmp.26ed5b5628.ll (mutant of float-fcmp.ll)fcmp_ueq-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-fcmp.40a7e6d9bb.ll (mutant of float-fcmp.ll)fcmp_ueq-mtriple=riscv64 -verify-machineinstrs
float-fcmp.561909aa41.ll (mutant of float-fcmp.ll)fcmp_ueq-mtriple=riscv32 -verify-machineinstrs
float-fcmp.665feab122.ll (mutant of float-fcmp.ll)fcmp_ueq-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
half-fcmp.10559a1e28.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32
half-fcmp.15a560c7c1.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f
half-fcmp.2e70733168.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-fcmp.91ec2afdd1.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-fcmp.ba0d768d05.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64
half-fcmp.c978671366.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64
half-fcmp.d62ec27d8e.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f
half-fcmp.f0112e10e3.ll (mutant of half-fcmp.ll)fcmp_ueq-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32
iabs.775622b7f9.ll (mutant of iabs.ll)abs128-mtriple=riscv64 -mattr=+zbb -verify-machineinstrs
iabs.b1244d39b5.ll (mutant of iabs.ll)abs128-mtriple=riscv32 -verify-machineinstrs
iabs.dba86d33b6.ll (mutant of iabs.ll)abs128-mtriple=riscv32 -mattr=+zbb -verify-machineinstrs
iabs.e46f310768.ll (mutant of iabs.ll)abs128-mtriple=riscv64 -verify-machineinstrs
inline-asm.086f400d02.ll (mutant of inline-asm.ll)modifier_z_nonzero-mtriple=riscv64 -verify-machineinstrs -no-integrated-as
inline-asm.8afdd9cdb6.ll (mutant of inline-asm.ll)modifier_z_nonzero-mtriple=riscv32 -verify-machineinstrs -no-integrated-as
qc-access-marking.7fc244e6fa.ll (mutant of qc-access-marking.ll)load_unsigned_byte_offset-mtriple=riscv32 -mattr=+xqcili,+relax -code-model=small -verify-machineinstrs
qc-access-marking.c56b73e651.ll (mutant of qc-access-marking.ll)load_unsigned_byte_offset-mtriple=riscv32 -mattr=+xqcili,+relax,+zca,+zcb -code-model=small -verify-machineinstrs
rv64f-float-convert.967ff17d85.ll (mutant of rv64f-float-convert.ll)bcvt_f32_to_zext_i32-mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs
rv64i-demanded-bits.99ac2a03d4.ll (mutant of rv64i-demanded-bits.ll)xori_sub_cse-mtriple=riscv64 -mattr=+m -verify-machineinstrs
rv64i-shift-sext.e5ab05f180.ll (mutant of rv64i-shift-sext.ll)test9-mtriple=riscv64 -verify-machineinstrs
rv64zfh-half-convert.868a469a86.ll (mutant of rv64zfh-half-convert.ll)bcvt_f16_to_zext_i16-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f

Generated 2026-10-15 08:05 UTC.