fallback: legalize: G

fallback: legalize: G_FDIV s16

Run:	explore-bc8218b282-20261015-075519
Kind:	fallback
Category:	legalize: G_FDIV s16
Occurrences:	39 in 22 configs, 7 test files
Snippet from:	half-arith.ll @fdiv_h via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define half @fdiv_h(half %a, half %b) #0 {
  %1 = fdiv half %a, %b
  ret half %1
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(s16) = G_FDIV %0:_, %1:_ (in function: fdiv_h)
warning: Instruction selection used fallback path for fdiv_h

Occurrences (39):

Input	Function	Config
half-arith.ll	fdiv_h	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-arith.ll	fdiv_h	`-mtriple=riscv32 -verify-machineinstrs`
half-arith.ll	fdiv_h	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-arith.ll	fdiv_h	`-mtriple=riscv64 -verify-machineinstrs`
rv32i-rv64i-half.ll	half_test	`-mtriple=riscv32 -verify-machineinstrs`
rv32i-rv64i-half.ll	half_test	`-mtriple=riscv64 -verify-machineinstrs`
inline-asm-zhinx-constraint-r.04a8720093.ll (mutant of inline-asm-zhinx-constraint-r.ll)	constraint_cf_half	`-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi=lp64`
inline-asm-zhinx-constraint-r.1e45dce41d.ll (mutant of inline-asm-zhinx-constraint-r.ll)	constraint_cf_half	`-mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs -target-abi=ilp32`
inline-asm-zhinx-constraint-r.43d969322e.ll (mutant of inline-asm-zhinx-constraint-r.ll)	constraint_cf_half	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
inline-asm-zhinx-constraint-r.96ad8e618a.ll (mutant of inline-asm-zhinx-constraint-r.ll)	constraint_cf_half	`-mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs -target-abi=lp64`
memcpy.39ce2ead48.ll (mutant of memcpy.ll)	aligned_memcpy4	`-mtriple=riscv32 -mattr=+unaligned-scalar-mem`
memcpy.7169205d0c.ll (mutant of memcpy.ll)	aligned_memcpy4	`-mtriple=riscv64 -mcpu=andes-ax45 -mtune=rocket`
memcpy.87d10fe304.ll (mutant of memcpy.ll)	aligned_memcpy4	`-mtriple=riscv64`
memcpy.afc77abdb3.ll (mutant of memcpy.ll)	aligned_memcpy4	`-mtriple=riscv32`
memcpy.b6a2b3ba4b.ll (mutant of memcpy.ll)	aligned_memcpy4	`-mtriple=riscv64 -mattr=+unaligned-scalar-mem`
memcpy.e3d9d97c4a.ll (mutant of memcpy.ll)	aligned_memcpy4	`-mtriple=riscv32 -mcpu=andes-a45 -mtune=rocket`
rv32i-rv64i-half.216bc04841.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv64 -verify-machineinstrs`
rv32i-rv64i-half.258207a9d9.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv64 -verify-machineinstrs`
rv32i-rv64i-half.3bdf8c4a92.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv64 -verify-machineinstrs`
rv32i-rv64i-half.8719e79d45.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv32 -verify-machineinstrs`
rv32i-rv64i-half.9b3ea3f189.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv32 -verify-machineinstrs`
rv32i-rv64i-half.9f92d0325d.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv32 -verify-machineinstrs`
rv32i-rv64i-half.eaddb37130.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv64 -verify-machineinstrs`
rv32i-rv64i-half.f0b470c7c5.ll (mutant of rv32i-rv64i-half.ll)	half_test	`-mtriple=riscv32 -verify-machineinstrs`
select-cond.1462ce7d21.ll (mutant of select-cond.ll)	select_i64_eq	`-mtriple=riscv32 -mattr=+xtheadcondmov -verify-machineinstrs`
select-cond.32af0ba56f.ll (mutant of select-cond.ll)	select_i64_eq	`-mtriple=riscv32 -mattr=+xqcics -verify-machineinstrs`
select-cond.6be191eda9.ll (mutant of select-cond.ll)	select_i64_eq	`-mtriple=riscv64 -verify-machineinstrs`
select-cond.6fa82cfd64.ll (mutant of select-cond.ll)	select_i64_eq	`-mtriple=riscv32 -verify-machineinstrs`
select-cond.951477b072.ll (mutant of select-cond.ll)	select_i64_eq	`-mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs`
select-cond.baba678741.ll (mutant of select-cond.ll)	select_i64_eq	`-mtriple=riscv32 -mattr=+xqcicm -verify-machineinstrs`
select-cond.e65d14a748.ll (mutant of select-cond.ll)	select_i64_eq	`-mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs`
xqcics.50c551ac6e.ll (mutant of xqcics.ll)	select_cc_example_ieqi_c3	`-mtriple=riscv32 -mattr=+xqcics,+xqcicm -verify-machineinstrs`
xqcics.69c5c95791.ll (mutant of xqcics.ll)	select_cc_example_ieqi_c3	`-mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs`
xqcics.815b56ccf6.ll (mutant of xqcics.ll)	select_cc_example_ieqi_c3	`-mtriple=riscv32 -mattr=+xqcics -verify-machineinstrs`
xqcics.a1f9effe94.ll (mutant of xqcics.ll)	select_cc_example_ieqi_c3	`-mtriple=riscv32 -verify-machineinstrs`
zfhmin-half-intrinsics.0e776d4fad.ll (mutant of zfhmin-half-intrinsics.ll)	lround_i32_f16	`-mtriple=riscv64 -mattr=+d -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d`
zfhmin-half-intrinsics.17e6664329.ll (mutant of zfhmin-half-intrinsics.ll)	lround_i32_f16	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
zfhmin-half-intrinsics.2f55ca5823.ll (mutant of zfhmin-half-intrinsics.ll)	lround_i32_f16	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
zfhmin-half-intrinsics.b80e6ea3ea.ll (mutant of zfhmin-half-intrinsics.ll)	lround_i32_f16	`-mtriple=riscv32 -mattr=+d -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d`

Generated 2026-10-15 08:05 UTC.