fallback: legalize: G_FPTOSI_SAT s32,s64

Run:explore-bc8218b282-20261015-075519
Kind:fallback
Category:legalize: G_FPTOSI_SAT s32,s64
Occurrences:40 in 6 configs, 2 test files
Snippet from:double-convert.ll @fcvt_w_d_sat via llvm-extract
Config:-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i32 @fcvt_w_d_sat(double %a) #0 {
start:
  %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
  ret i32 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fptosi.sat.i32.f64(double) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s32) = G_FPTOSI_SAT %0:_(s64) (in function: fcvt_w_d_sat)
warning: Instruction selection used fallback path for fcvt_w_d_sat

Occurrences (40):

InputFunctionConfig
double-convert.llfcvt_w_d_sat-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-convert.llfcvt_w_d_sat_sext-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-convert.llfcvt_w_d_sat-mtriple=riscv32 -verify-machineinstrs
double-convert.llfcvt_w_d_sat_sext-mtriple=riscv32 -verify-machineinstrs
double-convert.llfcvt_w_d_sat-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-convert.llfcvt_w_d_sat_sext-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-convert.llfcvt_w_d_sat-mtriple=riscv64 -verify-machineinstrs
double-convert.llfcvt_w_d_sat_sext-mtriple=riscv64 -verify-machineinstrs
double-round-conv-sat.lltest_floor_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.lltest_ceil_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.lltest_trunc_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.lltest_round_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.lltest_roundeven_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.lltest_rint_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.lltest_floor_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.lltest_ceil_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.lltest_trunc_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.lltest_round_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.lltest_roundeven_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.lltest_rint_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.lltest_floor_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.lltest_ceil_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.lltest_trunc_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.lltest_round_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.lltest_roundeven_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.lltest_rint_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.lltest_floor_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-round-conv-sat.lltest_ceil_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-round-conv-sat.lltest_trunc_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-round-conv-sat.lltest_round_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-round-conv-sat.lltest_roundeven_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-round-conv-sat.lltest_rint_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-round-conv-sat.12cb2c2f82.ll (mutant of double-round-conv-sat.ll)test_rint_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64
double-round-conv-sat.576fafa14b.ll (mutant of double-round-conv-sat.ll)test_round_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.5cdde6ad9c.ll (mutant of double-round-conv-sat.ll)test_rint_si32-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-round-conv-sat.756e0dab66.ll (mutant of double-round-conv-sat.ll)test_rint_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.7818ec2806.ll (mutant of double-round-conv-sat.ll)test_round_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.8eded3bcd6.ll (mutant of double-round-conv-sat.ll)test_rint_si32-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-round-conv-sat.e72797be09.ll (mutant of double-round-conv-sat.ll)test_round_si32-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
double-round-conv-sat.fac4606502.ll (mutant of double-round-conv-sat.ll)test_round_si32-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64

Generated 2026-10-15 08:05 UTC.