| Input | Function | Config |
|---|
| float-convert.ll | fcvt_lu_s_sat | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-convert.ll | fcvt_lu_s_sat | -mtriple=riscv32 -verify-machineinstrs |
| float-convert.ll | fcvt_lu_s_sat | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-convert.ll | fcvt_lu_s_sat | -mtriple=riscv64 -verify-machineinstrs |
| float-round-conv-sat.ll | test_floor_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.ll | test_ceil_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.ll | test_trunc_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.ll | test_round_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.ll | test_roundeven_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.ll | test_rint_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.ll | test_floor_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.ll | test_ceil_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.ll | test_trunc_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.ll | test_round_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.ll | test_roundeven_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.ll | test_rint_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.ll | test_floor_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.ll | test_ceil_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.ll | test_trunc_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.ll | test_round_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.ll | test_roundeven_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.ll | test_rint_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.ll | test_floor_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.ll | test_ceil_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.ll | test_trunc_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.ll | test_round_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.ll | test_roundeven_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.ll | test_rint_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-convert.2f0266b761.ll (mutant of float-convert.ll) | fcvt_lu_s_sat | -mtriple=riscv32 -verify-machineinstrs |
| float-convert.467861557d.ll (mutant of float-convert.ll) | fcvt_lu_s_sat | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-convert.86e3041192.ll (mutant of float-convert.ll) | fcvt_lu_s_sat | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-convert.d486b5ec48.ll (mutant of float-convert.ll) | fcvt_lu_s_sat | -mtriple=riscv64 -verify-machineinstrs |
| float-round-conv-sat.0cd2848103.ll (mutant of float-round-conv-sat.ll) | test_round_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.1544920deb.ll (mutant of float-round-conv-sat.ll) | test_round_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.1861b63ff0.ll (mutant of float-round-conv-sat.ll) | test_roundeven_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.1861b63ff0.ll (mutant of float-round-conv-sat.ll) | test_rint_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.2240af208f.ll (mutant of float-round-conv-sat.ll) | test_roundeven_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.2240af208f.ll (mutant of float-round-conv-sat.ll) | test_rint_ui64 | -mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f |
| float-round-conv-sat.4222d2a31c.ll (mutant of float-round-conv-sat.ll) | test_round_ui64 | -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f |
| float-round-conv-sat.8d2d01f33e.ll (mutant of float-round-conv-sat.ll) | test_roundeven_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.8d2d01f33e.ll (mutant of float-round-conv-sat.ll) | test_rint_ui64 | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 |
| float-round-conv-sat.a3e1f1ae06.ll (mutant of float-round-conv-sat.ll) | test_roundeven_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.a3e1f1ae06.ll (mutant of float-round-conv-sat.ll) | test_rint_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
| float-round-conv-sat.e97e4df65c.ll (mutant of float-round-conv-sat.ll) | test_round_ui64 | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 |
Generated 2026-10-15 08:05 UTC.