fallback: legalize: G_LOAD <8 x s8>,p0

Run:	explore-bc8218b282-20261015-075519
Kind:	fallback
Category:	legalize: G_LOAD <8 x s8>,p0
Occurrences:	122 in 52 configs, 26 test files
Snippet from:	rvp-unaligned-load-store.ll @test_store_v4i8_align1 via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+experimental-p`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define void @test_store_v4i8_align1(ptr %a_ptr, ptr %b_ptr) {
  %a = load <8 x i8>, ptr %a_ptr, align 8
  store <8 x i8> %a, ptr %b_ptr, align 1
  ret void
}

Reproduce:

llc -mtriple=riscv32 -mattr=+experimental-p -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+experimental-p -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<8 x s8>) = G_LOAD %0:_(p0) :: (load (<8 x s8>) from %ir.a_ptr) (in function: test_store_v4i8_align1)
warning: Instruction selection used fallback path for test_store_v4i8_align1

Occurrences (122) (first 50):

Input	Function	Config
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv32 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_load_v4i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align4	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv32 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv64 -mattr=+experimental-p`
rvp-unaligned-load-store.ll	test_load_v4i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v4i8_align4	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v4i8_align4	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align1	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_load_v8i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
rvp-unaligned-load-store.ll	test_store_v8i8_align2	`-mtriple=riscv64 -mattr=+experimental-p,+unaligned-scalar-mem`
atomic-fence.4c159027f4.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv64 -mattr=+a -verify-machineinstrs`
atomic-fence.5a947e02eb.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv32 -mattr=+a -verify-machineinstrs`
atomic-fence.9fed2fc072.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs`
atomic-fence.b07416c6c6.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv64 -verify-machineinstrs`
atomic-fence.b7cfbd1123.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs`
atomic-fence.b7f61819df.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs`
atomic-fence.cfffb22efe.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs`
atomic-fence.e546b97559.ll (mutant of atomic-fence.ll)	fence_acq_rel	`-mtriple=riscv32 -verify-machineinstrs`
atomic-rmw-minmax.15bf943e3c.ll (mutant of atomic-rmw-minmax.ll)	atomicrmw_umax_i32_seq_cst	`-mtriple=riscv32 -mattr=+b,+zalrsc,+permissive-zalrsc,+a -verify-machineinstrs`
atomic-rmw-minmax.9f6237c7a2.ll (mutant of atomic-rmw-minmax.ll)	atomicrmw_umax_i32_seq_cst	`-mtriple=riscv64 -mattr=+b,+zalrsc,+permissive-zalrsc,+a -verify-machineinstrs`
atomicrmw-cond-sub-clamp.31103bebc4.ll (mutant of atomicrmw-cond-sub-clamp.ll)	atomicrmw_usub_cond_i32	`-mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs`
atomicrmw-cond-sub-clamp.a534449bd0.ll (mutant of atomicrmw-cond-sub-clamp.ll)	atomicrmw_usub_cond_i32	`-mtriple=riscv32 -mattr=+a -verify-machineinstrs`
atomicrmw-cond-sub-clamp.a7c6a10025.ll (mutant of atomicrmw-cond-sub-clamp.ll)	atomicrmw_usub_cond_i32	`-mtriple=riscv32 -verify-machineinstrs`
atomicrmw-cond-sub-clamp.bc17b44506.ll (mutant of atomicrmw-cond-sub-clamp.ll)	atomicrmw_usub_cond_i32	`-mtriple=riscv64 -verify-machineinstrs`
atomicrmw-cond-sub-clamp.c0c07aff11.ll (mutant of atomicrmw-cond-sub-clamp.ll)	atomicrmw_usub_cond_i32	`-mtriple=riscv64 -mattr=+a,+ztso -verify-machineinstrs`
atomicrmw-cond-sub-clamp.ec91912094.ll (mutant of atomicrmw-cond-sub-clamp.ll)	atomicrmw_usub_cond_i32	`-mtriple=riscv64 -mattr=+a -verify-machineinstrs`
atomicrmw-uinc-udec-wrap.0652510ab0.ll (mutant of atomicrmw-uinc-udec-wrap.ll)	atomicrmw_uinc_wrap_i32	`-mtriple=riscv32 -mattr=+a,+ztso -verify-machineinstrs`
atomicrmw-uinc-udec-wrap.51c8ee3e7c.ll (mutant of atomicrmw-uinc-udec-wrap.ll)	atomicrmw_uinc_wrap_i32	`-mtriple=riscv64 -verify-machineinstrs`
atomicrmw-uinc-udec-wrap.7a17c67d42.ll (mutant of atomicrmw-uinc-udec-wrap.ll)	atomicrmw_uinc_wrap_i32	`-mtriple=riscv32 -verify-machineinstrs`
atomicrmw-uinc-udec-wrap.95246e84bf.ll (mutant of atomicrmw-uinc-udec-wrap.ll)	atomicrmw_uinc_wrap_i32	`-mtriple=riscv64 -mattr=+a -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.