fallback: legalize: G_OR <8 x s8>

Run:explore-bc8218b282-20261015-075519
Kind:fallback
Category:legalize: G_OR <8 x s8>
Occurrences:50 in 36 configs, 13 test files
Snippet from:rvp-simd-64.ll @test_or_b via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <8 x i8> @test_or_b(<8 x i8> %a, <8 x i8> %b) {
  %res = or <8 x i8> %a, %b
  ret <8 x i8> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<8 x s8>) = G_OR %0:_, %1:_ (in function: test_or_b)
warning: Instruction selection used fallback path for test_or_b

Occurrences (50):

InputFunctionConfig
rvp-bitreverse-zbkb.lltest_bitreverse_v8i8-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb,+zbkb -verify-machineinstrs
rvp-simd-64.lltest_or_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_orn_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
rvp-simd-64.lltest_bitreverse_v8i8-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
and-negpow2-cmp.d1630526b6.ll (mutant of and-negpow2-cmp.ll)test9-mtriple=riscv32
and-negpow2-cmp.e6bea09f1f.ll (mutant of and-negpow2-cmp.ll)test9-mtriple=riscv64
and.2a273de5a3.ll (mutant of and.ll)and64_0xfffffffffffff000-mtriple=riscv32 -verify-machineinstrs
and.9c70d19384.ll (mutant of and.ll)and64_0xfffffffffffff000-mtriple=riscv64 -verify-machineinstrs
calling-conv-p-ext-vector.74724fa07b.ll (mutant of calling-conv-p-ext-vector.ll)test_call_v4i8-mtriple=riscv32 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
double-br-fcmp.7ef9f81862.ll (mutant of double-br-fcmp.ll)br_fcmp_oeq-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32
double-br-fcmp.96a70ecf14.ll (mutant of double-br-fcmp.ll)br_fcmp_oeq-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
double-br-fcmp.a43f06c47a.ll (mutant of double-br-fcmp.ll)br_fcmp_oeq-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
fold-mem-offset.18605b0a77.ll (mutant of fold-mem-offset.ll)test_sh2add-mtriple=riscv32
fold-mem-offset.2d7f92a967.ll (mutant of fold-mem-offset.ll)test_sh2add-mtriple=riscv64 -mattr=+zba
fold-mem-offset.b32aa4d2f3.ll (mutant of fold-mem-offset.ll)test_sh2add-mtriple=riscv32 -mattr=+zba
fold-mem-offset.f53e875180.ll (mutant of fold-mem-offset.ll)test_sh2add-mtriple=riscv64
ghccc-without-f-reg.b480fc4e6b.ll (mutant of ghccc-without-f-reg.ll)caller_double-mtriple=riscv64 -mattr=+zfinx,+zdinx
half-br-fcmp.198549aa93.ll (mutant of half-br-fcmp.ll)br_fcmp_oeq-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f
half-br-fcmp.b7e60c145d.ll (mutant of half-br-fcmp.ll)br_fcmp_oeq-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-br-fcmp.e09d0e828b.ll (mutant of half-br-fcmp.ll)br_fcmp_oeq-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f
half-br-fcmp.f8c96dd7a8.ll (mutant of half-br-fcmp.ll)br_fcmp_oeq-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
neg-abs.36ca4754ef.ll (mutant of neg-abs.ll)expanded_neg_abs64-mtriple=riscv32 -mattr=+zbb -verify-machineinstrs
neg-abs.96a797c929.ll (mutant of neg-abs.ll)expanded_neg_abs64-mtriple=riscv32 -verify-machineinstrs
neg-abs.a54c746614.ll (mutant of neg-abs.ll)expanded_neg_abs64-mtriple=riscv64 -mattr=+zbb -verify-machineinstrs
neg-abs.b1798f4c9f.ll (mutant of neg-abs.ll)expanded_neg_abs64-mtriple=riscv64 -verify-machineinstrs
rvp-bitreverse-zbkb.aa0a2bbe55.ll (mutant of rvp-bitreverse-zbkb.ll)test_bitreverse_v8i8-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb,+zbkb -verify-machineinstrs
rvp-simd-64.28e6b76b57.ll (mutant of rvp-simd-64.ll)test_padd_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
select-binop-identity.0e0b03a2e5.ll (mutant of select-binop-identity.ll)xor_select_all_zeros_i32-mtriple=riscv64 -verify-machineinstrs
select-binop-identity.6f4470a01c.ll (mutant of select-binop-identity.ll)xor_select_all_zeros_i32-mtriple=riscv32 -mattr=+zicond -verify-machineinstrs
select-binop-identity.709ebcaf87.ll (mutant of select-binop-identity.ll)xor_select_all_zeros_i32-mtriple=riscv64 -mattr=+c,+conditional-cmv-fusion -verify-machineinstrs
select-binop-identity.b9abcbd4f1.ll (mutant of select-binop-identity.ll)xor_select_all_zeros_i32-mtriple=riscv64 -mattr=+zicond -verify-machineinstrs
select-binop-identity.c129819ad5.ll (mutant of select-binop-identity.ll)xor_select_all_zeros_i32-mtriple=riscv32 -verify-machineinstrs
select-binop-identity.fbb8de64ec.ll (mutant of select-binop-identity.ll)xor_select_all_zeros_i32-mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs
selectcc-to-shiftand.1bfc59f94e.ll (mutant of selectcc-to-shiftand.ll)sub_clamp_zero-mtriple=riscv32
selectcc-to-shiftand.22a361a21d.ll (mutant of selectcc-to-shiftand.ll)sub_clamp_zero-mtriple=riscv64 -mattr=+zbb
selectcc-to-shiftand.d9040ecabe.ll (mutant of selectcc-to-shiftand.ll)sub_clamp_zero-mtriple=riscv64
selectcc-to-shiftand.fe749f635d.ll (mutant of selectcc-to-shiftand.ll)sub_clamp_zero-mtriple=riscv32 -mattr=+zbb
vararg.125c722dc4.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv32 -verify-machineinstrs -frame-pointer=all
vararg.2197fceea0.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs
vararg.37387f1c7b.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv32 -verify-machineinstrs
vararg.3c899628dd.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv32 -mattr=+d -verify-machineinstrs
vararg.5d8ae27a32.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv32 -target-abi ilp32e -frame-pointer=all -verify-machineinstrs
vararg.6432b4cf3d.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv32 -mattr=+d -target-abi ilp32f -verify-machineinstrs
vararg.65a5a8d19e.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs
vararg.83ceb4ca77.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv64 -target-abi lp64e -frame-pointer=all -verify-machineinstrs
vararg.85809b2357.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv64 -verify-machineinstrs
vararg.ae793b38c5.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv64 -verify-machineinstrs -frame-pointer=all
vararg.c46e50fef6.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs
vararg.f70e601a07.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv64 -mattr=+d -target-abi lp64f -verify-machineinstrs
vararg.fa1b69edb1.ll (mutant of vararg.ll)va3_va_arg-mtriple=riscv64 -target-abi lp64e -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.