fallback: legalize: G_SITOFP s16,s32

Run:	explore-bc8218b282-20261015-075519
Kind:	fallback
Category:	legalize: G_SITOFP s16,s32
Occurrences:	92 in 18 configs, 3 test files
Snippet from:	half-convert.ll @fcvt_h_si via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define half @fcvt_h_si(i16 %a) #0 {
  %1 = sitofp i16 %a to half
  ret half %1
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(s16) = G_SITOFP %4:_(s32) (in function: fcvt_h_si)
warning: Instruction selection used fallback path for fcvt_h_si

Occurrences (92) (first 50):

Input	Function	Config
half-convert.ll	fcvt_h_si	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
half-convert.ll	fcvt_h_w	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
half-convert.ll	fcvt_h_si	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs`
half-convert.ll	fcvt_h_w	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs`
half-convert.ll	fcvt_h_si	`-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d`
half-convert.ll	fcvt_h_w	`-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d`
half-convert.ll	fcvt_h_si	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-convert.ll	fcvt_h_w	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-convert.ll	fcvt_h_si	`-mtriple=riscv32 -verify-machineinstrs`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv32 -verify-machineinstrs`
half-convert.ll	fcvt_h_w	`-mtriple=riscv32 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv32 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv32 -verify-machineinstrs`
half-convert.ll	fcvt_h_si	`-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs`
half-convert.ll	fcvt_h_w	`-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs`
half-convert.ll	fcvt_h_si	`-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs`
half-convert.ll	fcvt_h_w	`-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs`
half-convert.ll	fcvt_h_si	`-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d`
half-convert.ll	fcvt_h_w	`-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d`
half-convert.ll	fcvt_h_si	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-convert.ll	fcvt_h_w	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-convert.ll	fcvt_h_si	`-mtriple=riscv64 -verify-machineinstrs`
half-convert.ll	fcvt_h_si_signext	`-mtriple=riscv64 -verify-machineinstrs`
half-convert.ll	fcvt_h_w	`-mtriple=riscv64 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_load	`-mtriple=riscv64 -verify-machineinstrs`
half-convert.ll	fcvt_h_w_demanded_bits	`-mtriple=riscv64 -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.