fallback: legalize: G

fallback: legalize: G_SUB <4 x s16>

Run:	explore-bc8218b282-20261015-075519
Kind:	fallback
Category:	legalize: G_SUB <4 x s16>
Occurrences:	25 in 6 configs, 4 test files
Snippet from:	rvp-simd-64.ll @test_psub_h via llvm-extract
Config:	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
Local check:	reproduces at bc8218b282
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define <4 x i16> @test_psub_h(<4 x i16> %a, <4 x i16> %b) {
  %res = sub <4 x i16> %a, %b
  ret <4 x i16> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<4 x s16>) = G_SUB %0:_, %1:_ (in function: test_psub_h)
warning: Instruction selection used fallback path for test_psub_h

Occurrences (25):

Input	Function	Config
rvp-simd-32.ll	test_pwsub_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pwsubu_b	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_psub_h	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_pdif_h	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-64.ll	test_pdifu_h	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-widening-sub-acc.ll	test_pwsuba_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-widening-sub-acc.ll	test_pwsubau_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_1	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_2	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_power_of_two	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_one	`-mtriple=riscv32 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_1	`-mtriple=riscv32 -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_2	`-mtriple=riscv32 -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_power_of_two	`-mtriple=riscv32 -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_one	`-mtriple=riscv32 -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_1	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_2	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_power_of_two	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_one	`-mtriple=riscv64 -mattr=+m -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_1	`-mtriple=riscv64 -verify-machineinstrs`
urem-vector-lkk.ll	fold_urem_vec_2	`-mtriple=riscv64 -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_power_of_two	`-mtriple=riscv64 -verify-machineinstrs`
urem-vector-lkk.ll	dont_fold_urem_one	`-mtriple=riscv64 -verify-machineinstrs`
rvp-widening-sub-acc.0ff99530f0.ll (mutant of rvp-widening-sub-acc.ll)	test_pwsubau_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`
rvp-widening-sub-acc.562d48369b.ll (mutant of rvp-widening-sub-acc.ll)	test_pwsuba_v4i8	`-mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.