fallback: legalize: G_UREM <8 x s8>

Run:explore-bc8218b282-20261015-075519
Kind:fallback
Category:legalize: G_UREM <8 x s8>
Occurrences:24 in 21 configs, 9 test files
Snippet from:rvp-simd-64.ll @test_purem_b via llvm-extract
Config:-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <8 x i8> @test_purem_b(<8 x i8> %a, <8 x i8> %b) {
  %res = urem <8 x i8> %a, %b
  ret <8 x i8> %res
}

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(<8 x s8>) = G_UREM %0:_, %1:_ (in function: test_purem_b)
warning: Instruction selection used fallback path for test_purem_b

Occurrences (24):

InputFunctionConfig
rvp-simd-64.lltest_purem_b-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs
add-imm64-to-sub.2365868906.ll (mutant of add-imm64-to-sub.ll)sub_0xffffffffff-mtriple=riscv64 -mattr=+m,+zbb,+zbs
add-imm64-to-sub.64d4e69041.ll (mutant of add-imm64-to-sub.ll)sub_0xffffffffff-mtriple=riscv64 -mattr=+m,+zbb
fp128.0392cb2e82.ll (mutant of fp128.ll)fmaximum-mtriple=riscv32 -verify-machineinstrs
fp128.916453e436.ll (mutant of fp128.ll)fmaximum-mtriple=riscv64 -verify-machineinstrs
half-arith-strict.07cc945ed3.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs -disable-strictnode-mutation -target-abi lp64
half-arith-strict.9464aade40.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -disable-strictnode-mutation -target-abi ilp32
half-arith-strict.9a9b401547.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -disable-strictnode-mutation -target-abi lp64f
half-arith-strict.9abbdd94d1.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -disable-strictnode-mutation -target-abi ilp32f
half-arith-strict.b6a1bb16c9.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -disable-strictnode-mutation -target-abi ilp32f
half-arith-strict.d6bdc9d884.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -disable-strictnode-mutation -target-abi lp64f
half-arith-strict.d748e84db8.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -disable-strictnode-mutation -target-abi ilp32
half-arith-strict.d827544105.ll (mutant of half-arith-strict.ll)fmul_h-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -disable-strictnode-mutation -target-abi lp64
llvm.exp10.09ee145bcb.ll (mutant of llvm.exp10.ll)exp10_v3f16-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d
llvm.exp10.2bf6fd6277.ll (mutant of llvm.exp10.ll)exp10_v3f16-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d
shl-demanded.c80dcfe8be.ll (mutant of shl-demanded.ll)sext_shl_trunc_smaller-mtriple=riscv32 -verify-machineinstrs
shl-demanded.eb8b9e293b.ll (mutant of shl-demanded.ll)sext_shl_trunc_smaller-mtriple=riscv64 -verify-machineinstrs
simplify-condbr.8d9d3f4b26.ll (mutant of simplify-condbr.ll)S_regrepeat-mtriple=riscv64 -verify-machineinstrs
usub_sat.35c852c5bf.ll (mutant of usub_sat.ll)func16-mtriple=riscv32 -mattr=+m,+zbb,+v
usub_sat.55192cfe18.ll (mutant of usub_sat.ll)func16-mtriple=riscv32 -mattr=+m,+v
usub_sat.67e2d4d110.ll (mutant of usub_sat.ll)func16-mtriple=riscv64 -mattr=+m,+v
usub_sat.7d1533af6c.ll (mutant of usub_sat.ll)func16-mtriple=riscv64 -mattr=+m,+zbb,+v
xtheadmac.4c61fec2e0.ll (mutant of xtheadmac.ll)mula_i64-mtriple=riscv32 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs
xtheadmac.657014bee7.ll (mutant of xtheadmac.ll)mula_i64-mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.