| Run: | explore-bc8218b282-20261015-075519 |
| Kind: | fallback |
| Category: | legalize: G_VECREDUCE_ADD s16,<16 x s16> |
| Occurrences: | 10 in 2 configs, 1 test files |
| Snippet from: | double_reduct.ll @add_ext_i16 via llvm-extract |
| Config: | -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs |
| Local check: | reproduces at bc8218b282 |
| Compiler Explorer: | not uploaded (over --godbolt-limit or disabled) |
define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {
%ae = zext <16 x i8> %a to <16 x i16>
%be = zext <16 x i8> %b to <16 x i16>
%r1 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %ae)
%r2 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %be)
%r = add i16 %r1, %r2
ret i16 %r
}
; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>) #0
attributes #0 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o - llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs -global-isel=0 snippet.ll -o -
remark: <unknown>:0:0: unable to legalize instruction: %7:_(s16) = G_VECREDUCE_ADD %5:_(<16 x s16>) (in function: add_ext_i16) warning: Instruction selection used fallback path for add_ext_i16
| Input | Function | Config |
|---|---|---|
| double_reduct.ll | add_ext_i16 | -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs |
| double_reduct.ll | add_ext_v32i16 | -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs |
| double_reduct.ll | add_ext_i16 | -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs |
| double_reduct.ll | add_ext_v32i16 | -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs |
| double_reduct.4059867fcb.ll (mutant of double_reduct.ll) | add_ext_i16 | -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs |
| double_reduct.4ac87308f8.ll (mutant of double_reduct.ll) | add_ext_v32i16 | -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs |
| double_reduct.e04650ceb8.ll (mutant of double_reduct.ll) | add_ext_v32i16 | -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs |
| double_reduct.ec8d681823.ll (mutant of double_reduct.ll) | add_ext_v32i16 | -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d -verify-machineinstrs |
| double_reduct.f74a19d075.ll (mutant of double_reduct.ll) | add_ext_i16 | -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs |
| double_reduct.fcfec5b501.ll (mutant of double_reduct.ll) | add_ext_v32i16 | -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d -verify-machineinstrs |
Generated 2026-10-15 08:05 UTC.