regression: +91 insts: add (emit-x8-as-fp.ll)

Snippet:

@G = external global i32

; Function Attrs: noinline nounwind optnone
define signext i32 @add(i32 %0, i32 %1) #0 {
  %A = alloca i1, align 1
  %C = icmp sgt i32 %1, %1
  store i1 false, ptr %A, align 1
  %3 = alloca i32, align 4
  %L = load i8, ptr %3, align 1
  %4 = alloca i32, align 4
  %B = udiv i32 %0, 0
  store i32 %B, ptr %3, align 4
  switch i8 %L, label %SW_D [
    i8 -34, label %SW_C
    i8 -28, label %SW_C1
    i8 74, label %SW_C2
    i8 -75, label %SW_C3
    i8 9, label %SW_C4
    i8 127, label %SW_C5
    i8 96, label %SW_C6
    i8 21, label %SW_C7
  ]

BB:                                               ; preds = %SW_C7, %SW_C6, %SW_C1, %SW_C
  store i32 %1, ptr %4, align 4
  %5 = load i32, ptr %3, align 4
  %6 = load i32, ptr %4, align 4
  %7 = add nsw i32 %5, %6
  ret i32 %7

SW_D:                                             ; preds = %2
  ret i32 %1

SW_C:                                             ; preds = %2
  br label %BB

SW_C1:                                            ; preds = %2
  br label %BB

SW_C2:                                            ; preds = %2
  ret i32 65536

SW_C3:                                            ; preds = %2
  ret i32 %B

SW_C4:                                            ; preds = %2
  ret i32 %0

SW_C5:                                            ; preds = %2
  %LGV = load i32, ptr @G, align 4
  ret i32 %LGV

SW_C6:                                            ; preds = %2
  br label %BB

SW_C7:                                            ; preds = %SW_C7, %2
  br i1 %C, label %BB, label %SW_C7
}

attributes #0 = { noinline nounwind optnone "frame-pointer"="all" }

Reproduce:

llc -mtriple=riscv64 -M emit-x8-as-fp -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv64 -M emit-x8-as-fp -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,98 +1,192 @@
-addi sp, sp, -32
-sd ra, 24(sp)
-sd fp, 16(sp)
-addi fp, sp, 32
-sb zero, 15(sp)
-lbu a2, 8(sp)
-li a3, 181
-beq a2, a3, .L0
+addi sp, sp, -128
+sd ra, 120(sp)
+sd fp, 112(sp)
+sd s1, 104(sp)
+sd s2, 96(sp)
+sd s3, 88(sp)
+sd s4, 80(sp)
+sd s5, 72(sp)
+sd s6, 64(sp)
+sd s7, 56(sp)
+sd s8, 48(sp)
+sd s9, 40(sp)
+sd s10, 32(sp)
+sd s11, 24(sp)
+addi fp, sp, 128
+mv s2, a0
+mv s1, a1
+li s6, 21
+li s9, 96
+li s4, 127
+li s5, 74
+li s11, -28
+li s8, 9
+lui s7, %hi(G)
+addi s7, s7, %lo(G)
+sext.w s10, s1
+sb zero, 23(sp)
+lbu s3, 16(sp)
+slli a0, s2, 32
+srli a0, a0, 32
+li a1, 0
+call __udivdi3
+sw a0, 16(sp)
+slli a1, s3, 56
+srai a1, a1, 56
+bge a1, s6, .L0
 j .L1
 .L1:
-zext.b a3, a2
-li a4, 222
-beq a3, a4, .L2
+slli a1, s3, 56
+srai a1, a1, 56
+bge a1, s11, .L2
 j .L3
 .L3:
-zext.b a3, a2
-li a4, 228
-beq a3, a4, .L4
+li a1, 181
+beq s3, a1, .L4
 j .L5
 .L5:
-zext.b a3, a2
-li a4, 9
-beq a3, a4, .L6
+li a0, 222
+beq s3, a0, .L6
 j .L7
-.L7:
-zext.b a0, a2
-li a3, 21
-beq a0, a3, .L8
+.L2:
+li a0, 228
+beq s3, a0, .L8
 j .L9
 .L9:
-zext.b a0, a2
-li a3, 74
-beq a0, a3, .L10
-j .L11
+beq s3, s8, .L10
+j .L7
+.L0:
+slli a0, s3, 56
+srai a0, a0, 56
+bge a0, s9, .L11
+j .L12
+.L12:
+beq s3, s6, .L13
+j .L14
+.L14:
+beq s3, s5, .L15
+j .L7
 .L11:
-zext.b a0, a2
-li a3, 96
-beq a0, a3, .L12
-j .L13
+beq s3, s9, .L16
+j .L17
+.L17:
+beq s3, s4, .L18
+j .L7
 .L13:
-zext.b a0, a2
-li a2, 127
-beq a0, a2, .L14
-j .L15
-.L8:
-j .L16
-.L17:
-j .L18
-.L18:
-sw a1, 4(sp)
-lw a0, 8(sp)
-lw a1, 4(sp)
+j .L19
+.L20:
+.L21:
+sw s1, 12(sp)
+lw a0, 16(sp)
+lw a1, 12(sp)
 addw a0, a0, a1
-ld ra, 24(sp)
-ld fp, 16(sp)
-addi sp, sp, 32
+sext.w a0, a0
+ld ra, 120(sp)
+ld fp, 112(sp)
+ld s1, 104(sp)
+ld s2, 96(sp)
+ld s3, 88(sp)
+ld s4, 80(sp)
+ld s5, 72(sp)
+ld s6, 64(sp)
+ld s7, 56(sp)
+ld s8, 48(sp)
+ld s9, 40(sp)
+ld s10, 32(sp)
+ld s11, 24(sp)
+addi sp, sp, 128
 ret
-.L15:
-sext.w a0, a1
-ld ra, 24(sp)
-ld fp, 16(sp)
-addi sp, sp, 32
-ret
-.L2:
-j .L18
-.L4:
-j .L18
-.L10:
-lui a0, 16
-ld ra, 24(sp)
-ld fp, 16(sp)
-addi sp, sp, 32
-ret
-.L0:
-sext.w a0, a0
-ld ra, 24(sp)
-ld fp, 16(sp)
-addi sp, sp, 32
+.L7:
+sext.w a0, s1
+ld ra, 120(sp)
+ld fp, 112(sp)
+ld s1, 104(sp)
+ld s2, 96(sp)
+ld s3, 88(sp)
+ld s4, 80(sp)
+ld s5, 72(sp)
+ld s6, 64(sp)
+ld s7, 56(sp)
+ld s8, 48(sp)
+ld s9, 40(sp)
+ld s10, 32(sp)
+ld s11, 24(sp)
+addi sp, sp, 128
 ret
 .L6:
+j .L21
+.L8:
+j .L21
+.L15:
+lui a0, 16
+ld ra, 120(sp)
+ld fp, 112(sp)
+ld s1, 104(sp)
+ld s2, 96(sp)
+ld s3, 88(sp)
+ld s4, 80(sp)
+ld s5, 72(sp)
+ld s6, 64(sp)
+ld s7, 56(sp)
+ld s8, 48(sp)
+ld s9, 40(sp)
+ld s10, 32(sp)
+ld s11, 24(sp)
+addi sp, sp, 128
+ret
+.L4:
 sext.w a0, a0
-ld ra, 24(sp)
-ld fp, 16(sp)
-addi sp, sp, 32
+ld ra, 120(sp)
+ld fp, 112(sp)
+ld s1, 104(sp)
+ld s2, 96(sp)
+ld s3, 88(sp)
+ld s4, 80(sp)
+ld s5, 72(sp)
+ld s6, 64(sp)
+ld s7, 56(sp)
+ld s8, 48(sp)
+ld s9, 40(sp)
+ld s10, 32(sp)
+ld s11, 24(sp)
+addi sp, sp, 128
 ret
-.L14:
-lui a0, %hi(G)
-lw a0, %lo(G)(a0)
-ld ra, 24(sp)
-ld fp, 16(sp)
-addi sp, sp, 32
+.L10:
+sext.w a0, s2
+ld ra, 120(sp)
+ld fp, 112(sp)
+ld s1, 104(sp)
+ld s2, 96(sp)
+ld s3, 88(sp)
+ld s4, 80(sp)
+ld s5, 72(sp)
+ld s6, 64(sp)
+ld s7, 56(sp)
+ld s8, 48(sp)
+ld s9, 40(sp)
+ld s10, 32(sp)
+ld s11, 24(sp)
+addi sp, sp, 128
 ret
-.L12:
-j .L18
+.L18:
+lw a0, 0(s7)
+ld ra, 120(sp)
+ld fp, 112(sp)
+ld s1, 104(sp)
+ld s2, 96(sp)
+ld s3, 88(sp)
+ld s4, 80(sp)
+ld s5, 72(sp)
+ld s6, 64(sp)
+ld s7, 56(sp)
+ld s8, 48(sp)
+ld s9, 40(sp)
+ld s10, 32(sp)
+ld s11, 24(sp)
+addi sp, sp, 128
+ret
 .L16:
-andi a0, zero, 1
-bnez a0, .L17
-j .L16
+j .L21
+.L19:
+blt s10, s10, .L20
+j .L19

Occurrences (1):

Generated 2026-10-15 08:05 UTC.