regression: +101 insts: stest_f16i32 (fpclamptosat.ll)

Snippet:

@G.1 = external global i32
@G.2 = external global i1

define i32 @stest_f16i32(half %x) {
entry:
  %A7 = alloca i1, align 1
  store i1 true, ptr %A7, align 1
  %A = alloca i128, align 8
  store i128 0, ptr %A, align 4
  %conv = fptosi half %x to i64
  %0 = icmp slt i64 %conv, 2147483647
  %spec.store.select = select i1 %0, i64 %conv, i64 2147483647
  %1 = icmp sgt i64 %spec.store.select, -2147483648
  %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 -2147483648
  %L = load i128, ptr %A, align 4
  switch i128 %L, label %SW_D [
    i128 16497444310075683671, label %SW_C
    i128 9719112835208792309, label %SW_C1
    i128 8218851618281377479, label %SW_C2
    i128 1616212072766074706, label %SW_C3
    i128 15853715059431310258, label %SW_C4
    i128 10293132691202480369, label %SW_C5
    i128 3329681376119731708, label %SW_C6
  ]

BB:                                               ; preds = %SW_C6, %SW_C5, %SW_C2, %SW_C1, %SW_C, %SW_D
  %conv6 = trunc i64 %spec.store.select7 to i32
  ret i32 %conv6

SW_D:                                             ; preds = %SW_D, %entry
  br i1 %0, label %SW_D, label %BB

SW_C:                                             ; preds = %entry
  br label %BB

SW_C1:                                            ; preds = %entry
  br label %BB

SW_C2:                                            ; preds = %SW_C2, %entry
  %L8 = load i1, ptr %A7, align 1
  br i1 %L8, label %SW_C2, label %BB

SW_C3:                                            ; preds = %entry
  ret i32 65536

SW_C4:                                            ; preds = %entry
  %LGV = load i32, ptr @G.1, align 4
  ret i32 %LGV

SW_C5:                                            ; preds = %SW_C5, %entry
  %LGV9 = load i1, ptr @G.2, align 1
  br i1 %LGV9, label %SW_C5, label %BB

SW_C6:                                            ; preds = %entry
  br label %BB
}

Reproduce:

llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel snippet.ll -o -
llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,59 +1,174 @@
 addi sp, sp, -32
 sw ra, 28(sp)
+sw s0, 24(sp)
+sw s1, 20(sp)
+lui s0, 524288
 li a0, 1
-sb a0, 27(sp)
-sw zero, 8(sp)
-sw zero, 12(sp)
-sw zero, 16(sp)
-sw zero, 20(sp)
-call __extendhfsf2
-call __fixsfdi
-lui a3, 524288
-addi a4, a3, -1
+addi s1, s0, -1
+sb a0, 19(sp)
+mv a0, sp
+sw zero, 4(a0)
+sw zero, 8(a0)
+sw zero, 12(a0)
+sw zero, 0(sp)
+call __fixhfdi
 beqz a1, .L0
 srli a2, a1, 31
-j .L1
+li a3, -1
+beqz a2, .L1
+j .L2
 .L0:
-sltu a2, a0, a4
+sltu a2, a0, s1
+li a3, -1
+bnez a2, .L2
 .L1:
-neg a5, a2
-and a1, a5, a1
-bnez a2, .L2
-mv a0, a4
+li a1, 0
+mv a0, s1
 .L2:
-li a4, -1
-beq a1, a4, .L3
-srli a1, a1, 31
+lui a4, 552468
+beq a1, a3, .L3
+slti a1, a1, 0
 xori a1, a1, 1
-beqz a1, .L4
-j .L5
+j .L4
 .L3:
-sltu a1, a3, a0
+sltu a1, s0, a0
+.L4:
+lui a6, 174325
+addi a5, a4, -1631
 bnez a1, .L5
-.L4:
 lui a0, 524288
 .L5:
-j .L6
+lw a1, 4(sp)
+lw a3, 0(sp)
+lw a4, 8(sp)
+addi a7, a6, -1803
+beq a1, a5, .L6
+sltu a6, a1, a5
 j .L7
+.L6:
+sltu a6, a3, a7
+.L7:
+xori t2, a6, 1
+lw a6, 12(sp)
+sltiu t0, a4, 0
+bnez a4, .L8
+slti t1, a6, 0
+bnez a6, .L9
+.L10:
+beqz t2, .L11
+.L12:
+lui t2, 901179
+lui t3, 621216
+addi t2, t2, 1497
+addi t3, t3, 946
+beq a1, t2, .L13
+sltu t4, a1, t2
+xori t4, t4, 1
+bnez a4, .L14
+j .L15
+.L8:
+xori t2, t0, 1
+slti t1, a6, 0
+beqz a6, .L10
+.L9:
+xori t2, t1, 1
+bnez t2, .L12
+.L11:
+lui a5, 192183
+lui a7, 91871
+addi a5, a5, -174
+addi a7, a7, 81
+xor a5, a3, a5
+xor a7, a1, a7
+or a5, a5, a7
+or a4, a4, a6
+or a5, a5, a4
+beqz a5, .L16
+lui a5, 1011099
+lui a6, 189270
+addi a5, a5, 1532
+addi a6, a6, 1937
+xor a5, a3, a5
+xor a6, a1, a6
+or a5, a5, a6
+or a5, a5, a4
+beqz a5, .L17
+lui a5, 398565
+lui a6, 467188
+addi a5, a5, -313
+addi a6, a6, -1536
+xor a3, a3, a5
+xor a1, a1, a6
+or a1, a3, a1
+or a1, a1, a4
+bnez a1, .L18
+lbu a1, 19(sp)
+andi a1, a1, 1
+.L19:
+bnez a1, .L19
+j .L17
+.L13:
+sltu t4, a3, t3
+xori t4, t4, 1
+beqz a4, .L15
+.L14:
+xori t4, t0, 1
+.L15:
+bnez a6, .L20
+bnez t4, .L21
+.L22:
+xor a7, a3, a7
+xor a5, a1, a5
+or a5, a7, a5
+or a4, a4, a6
+or a5, a5, a4
+beqz a5, .L17
+lui a5, 741722
+lui a6, 585097
+addi a5, a5, -1807
+addi a6, a6, -603
+xor a3, a3, a5
+xor a1, a1, a6
+or a1, a3, a1
+or a1, a1, a4
+bnez a1, .L18
 lui a1, %hi(G.2)
 lbu a1, %lo(G.2)(a1)
-.L8:
-bnez a1, .L8
-j .L9
-.L6:
-j .L7
-lbu a1, 27(sp)
-.L10:
-bnez a1, .L10
-j .L9
-.L7:
-bnez a2, .L7
-j .L9
+andi a1, a1, 1
+.L23:
+bnez a1, .L23
+j .L17
+.L20:
+xori t4, t1, 1
+beqz t4, .L22
+.L21:
+xor a5, a3, t3
+xor a7, a1, t2
+or a5, a5, a7
+or a4, a4, a6
+or a5, a5, a4
+beqz a5, .L24
+lui a5, 376219
+lui a6, 937771
+addi a5, a5, 855
+addi a6, a6, 561
+xor a3, a3, a5
+xor a1, a1, a6
+or a1, a3, a1
+or a1, a1, a4
+beqz a1, .L17
+.L18:
+bnez a2, .L18
+j .L17
+.L16:
 lui a0, 16
-j .L9
+j .L17
+.L24:
 lui a0, %hi(G.1)
 lw a0, %lo(G.1)(a0)
-.L9:
+.L17:
 lw ra, 28(sp)
+lw s0, 24(sp)
+lw s1, 20(sp)
 addi sp, sp, 32
 ret

Occurrences (1):

Generated 2026-10-15 08:05 UTC.