regression: +99 insts: mulhs (mul.ll)

Run:explore-bc8218b282-20261015-075519
Kind:regression
Category:+99 insts: mulhs (mul.ll)
Occurrences:1 in 1 configs, 1 test files
Snippet from:mul.c8ad47c3f5.ll (mutant of mul.ll) @mulhs via llvm-extract
Config:-mtriple=riscv32 -verify-machineinstrs
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

@G = external global i1

; Function Attrs: nounwind
define i32 @mulhs(i32 %a, i32 %b) #0 {
  %A11 = alloca i1, align 1
  store i1 true, ptr %A11, align 1
  %A9 = alloca i1, align 1
  store i1 true, ptr %A9, align 1
  %A7 = alloca i1, align 1
  store i1 false, ptr %A7, align 1
  %A = alloca i128, align 8
  store i128 0, ptr %A, align 4
  %1 = sext i32 %a to i64
  %2 = sext i32 %b to i64
  %3 = mul i64 %1, %2
  %4 = lshr i64 %3, 32
  %L = load i128, ptr %A, align 4
  switch i128 %L, label %SW_D [
    i128 16497444310075683671, label %SW_C
    i128 9719112835208792309, label %SW_C1
    i128 8218851618281377479, label %SW_C2
    i128 1616212072766074706, label %SW_C3
    i128 15853715059431310258, label %SW_C4
    i128 10293132691202480369, label %SW_C5
    i128 3329681376119731708, label %SW_C6
  ]

BB:                                               ; preds = %SW_C6, %SW_C5, %SW_C4, %SW_C3, %SW_C2, %SW_C1, %SW_C, %SW_D
  %5 = trunc i64 %4 to i32
  ret i32 %5

SW_D:                                             ; preds = %SW_D, %0
  %L8 = load i1, ptr %A7, align 1
  br i1 %L8, label %SW_D, label %BB

SW_C:                                             ; preds = %0
  br label %BB

SW_C1:                                            ; preds = %SW_C1, %0
  %LGV = load i1, ptr @G, align 1
  %L10 = load i1, ptr %A9, align 1
  br i1 %L10, label %SW_C1, label %BB

SW_C2:                                            ; preds = %0
  br label %BB

SW_C3:                                            ; preds = %0
  br label %BB

SW_C4:                                            ; preds = %SW_C4, %0
  %L12 = load i1, ptr %A11, align 1
  br i1 %L12, label %BB, label %SW_C4

SW_C5:                                            ; preds = %0
  br label %BB

SW_C6:                                            ; preds = %0
  br label %BB
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,37 +1,149 @@
 addi sp, sp, -32
 sw ra, 28(sp)
+sw s0, 24(sp)
+sw s1, 20(sp)
 mv a2, a1
 li a1, 1
-sb a1, 27(sp)
-sb a1, 26(sp)
-sb zero, 25(sp)
-sw zero, 8(sp)
-sw zero, 12(sp)
-sw zero, 16(sp)
-sw zero, 20(sp)
+lui a3, 174325
+lui a4, 552468
+addi s0, a3, -1803
+addi s1, a4, -1631
+sb a1, 19(sp)
+sb a1, 18(sp)
+sb zero, 17(sp)
+mv a1, sp
+sw zero, 4(a1)
+sw zero, 8(a1)
+sw zero, 12(a1)
+sw zero, 0(sp)
 srai a1, a0, 31
 srai a3, a2, 31
 call __muldi3
+lw a2, 4(sp)
+lw a3, 0(sp)
+lw a4, 8(sp)
 mv a0, a1
-j .L0
+beq a2, s1, .L0
+sltu a1, a2, s1
 j .L1
-lbu a1, 26(sp)
+.L0:
+sltu a1, a3, s0
+.L1:
+xori a5, a1, 1
+lw a1, 12(sp)
+sltiu a7, a4, 0
+bnez a4, .L2
+slti t0, a1, 0
+bnez a1, .L3
+.L4:
+beqz a5, .L5
+.L6:
+lui a5, 901179
+lui a6, 621216
+addi a5, a5, 1497
+addi a6, a6, 946
+beq a2, a5, .L7
+sltu t1, a2, a5
+xori t1, t1, 1
+bnez a4, .L8
+j .L9
 .L2:
-bnez a1, .L2
-j .L3
-.L0:
-.L1:
-j .L4
-j .L4
-lbu a1, 27(sp)
+xori a5, a7, 1
+slti t0, a1, 0
+beqz a1, .L4
+.L3:
+xori a5, t0, 1
+bnez a5, .L6
 .L5:
-beqz a1, .L5
-j .L3
-.L4:
-lbu a1, 25(sp)
-.L6:
-bnez a1, .L6
-.L3:
+lui a5, 192183
+lui a6, 91871
+addi a5, a5, -174
+addi a6, a6, 81
+xor a5, a3, a5
+xor a6, a2, a6
+or a5, a5, a6
+or a1, a4, a1
+or a5, a5, a1
+beqz a5, .L10
+lui a4, 1011099
+lui a5, 189270
+addi a4, a4, 1532
+addi a5, a5, 1937
+xor a4, a3, a4
+xor a5, a2, a5
+or a4, a4, a5
+or a4, a4, a1
+beqz a4, .L10
+lui a4, 398565
+lui a5, 467188
+addi a4, a4, -313
+addi a5, a5, -1536
+j .L11
+.L7:
+sltu t1, a3, a6
+xori t1, t1, 1
+beqz a4, .L9
+.L8:
+xori t1, a7, 1
+.L9:
+bnez a1, .L12
+bnez t1, .L13
+.L14:
+xor s0, a3, s0
+xor s1, a2, s1
+or s0, s0, s1
+or a1, a4, a1
+or s0, s0, a1
+beqz s0, .L15
+lui a4, 741722
+lui a5, 585097
+addi a4, a4, -1807
+addi a5, a5, -603
+.L11:
+xor a3, a3, a4
+xor a2, a2, a5
+or a2, a3, a2
+or a1, a2, a1
+beqz a1, .L10
+j .L16
+.L12:
+xori t1, t0, 1
+beqz t1, .L14
+.L13:
+lui a7, 376219
+lui t0, 937771
+addi a7, a7, 855
+addi t0, t0, 561
+xor a7, a3, a7
+xor t0, a2, t0
+or a7, a7, t0
+or a1, a4, a1
+or a4, a7, a1
+beqz a4, .L10
+xor a3, a3, a6
+xor a2, a2, a5
+or a2, a3, a2
+or a1, a2, a1
+bnez a1, .L16
+lbu a1, 19(sp)
+andi a1, a1, 1
+.L17:
+beqz a1, .L17
+j .L10
+.L15:
+lbu a1, 18(sp)
+andi a1, a1, 1
+.L18:
+bnez a1, .L18
+j .L10
+.L16:
+lbu a1, 17(sp)
+andi a1, a1, 1
+.L19:
+bnez a1, .L19
+.L10:
 lw ra, 28(sp)
+lw s0, 24(sp)
+lw s1, 20(sp)
 addi sp, sp, 32
 ret

Occurrences (1):

InputFunctionConfig
mul.c8ad47c3f5.ll (mutant of mul.ll)mulhs-mtriple=riscv32 -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.