regression: +177 insts: foo (reserved-regs.ll)

Snippet:

@var = external global [32 x i64]
@G = external global i16
@G.2 = external global i64

define void @foo() {
  %B = add i128 170141183460469231731687303715884105727, 0
  %1 = load volatile [32 x i64], ptr @var, align 4
  %E = extractvalue [32 x i64] %1, 31
  store volatile [32 x i64] %1, ptr @var, align 4
  store i128 %B, ptr poison, align 4
  %B1 = and i16 42, 0
  store i16 %B1, ptr @G, align 2
  store i64 %E, ptr @G.2, align 4
  ret void
}

Reproduce:

llc -mtriple=riscv64 -mattr=+reserve-x21 -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv64 -mattr=+reserve-x21 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,114 +1,291 @@
-addi sp, sp, -144
-sd ra, 136(sp)
-sd s0, 128(sp)
-sd s1, 120(sp)
-sd s2, 112(sp)
-sd s3, 104(sp)
-sd s4, 96(sp)
-sd s6, 88(sp)
-sd s7, 80(sp)
-sd s8, 72(sp)
-sd s9, 64(sp)
-sd s10, 56(sp)
-sd s11, 48(sp)
+addi sp, sp, -192
+sd ra, 184(sp)
+sd s0, 176(sp)
+sd s1, 168(sp)
+sd s2, 160(sp)
+sd s3, 152(sp)
+sd s4, 144(sp)
+sd s6, 136(sp)
+sd s7, 128(sp)
+sd s8, 120(sp)
+sd s9, 112(sp)
+sd s10, 104(sp)
+sd s11, 96(sp)
 lui a0, %hi(var)
 addi a0, a0, %lo(var)
-ld a1, 0(a0)
-sd a1, 40(sp)
-ld a1, 8(a0)
+lwu a1, 0(a0)
+lw a2, 4(a0)
+lwu a3, 8(a0)
+lw a4, 12(a0)
+lwu a5, 16(a0)
+lw a6, 20(a0)
+lwu a7, 24(a0)
+lw t0, 28(a0)
+slli a2, a2, 32
+slli a4, a4, 32
+slli a6, a6, 32
+slli t0, t0, 32
+or a1, a2, a1
+sd a1, 80(sp)
+or a3, a4, a3
+sd a3, 88(sp)
+lwu a1, 32(a0)
+lw a2, 36(a0)
+lwu a3, 40(a0)
+lw a4, 44(a0)
+lwu t1, 48(a0)
+lw t2, 52(a0)
+lwu t3, 56(a0)
+lw t4, 60(a0)
+or a5, a6, a5
+sd a5, 48(sp)
+or a5, t0, a7
+sd a5, 56(sp)
+slli a2, a2, 32
+slli a4, a4, 32
+or a1, a2, a1
+sd a1, 64(sp)
+or a3, a4, a3
+sd a3, 72(sp)
+slli t2, t2, 32
+slli t4, t4, 32
+lwu a1, 64(a0)
+lw a2, 68(a0)
+lwu a3, 72(a0)
+lw a4, 76(a0)
+lwu a5, 80(a0)
+lw a6, 84(a0)
+lwu t5, 88(a0)
+lw t6, 92(a0)
+or a7, t2, t1
+sd a7, 16(sp)
+or a7, t4, t3
+sd a7, 24(sp)
+slli a2, a2, 32
+slli a4, a4, 32
+or a1, a2, a1
 sd a1, 32(sp)
-ld a1, 16(a0)
-sd a1, 24(sp)
-ld a1, 24(a0)
-sd a1, 16(sp)
-ld a1, 32(a0)
+or a3, a4, a3
+sd a3, 40(sp)
+slli a6, a6, 32
+slli a1, t6, 32
+lwu a2, 96(a0)
+lw a3, 100(a0)
+lwu a4, 104(a0)
+lw t3, 108(a0)
+lwu s0, 112(a0)
+lw s1, 116(a0)
+lwu s2, 120(a0)
+lw s3, 124(a0)
+or t6, a6, a5
+or t5, a1, t5
+slli a3, a3, 32
+slli t3, t3, 32
+or a2, a3, a2
+sd a2, 0(sp)
+or a1, t3, a4
 sd a1, 8(sp)
-ld a1, 40(a0)
-sd a1, 0(sp)
-ld a7, 48(a0)
-ld t0, 56(a0)
-ld t1, 64(a0)
-ld t2, 72(a0)
-ld t3, 80(a0)
-ld t4, 88(a0)
-ld t5, 96(a0)
-ld t6, 104(a0)
-ld s0, 112(a0)
-ld s1, 120(a0)
-ld s2, 128(a0)
-ld s3, 136(a0)
-ld s4, 144(a0)
-ld s6, 152(a0)
-ld s7, 160(a0)
-ld s8, 168(a0)
-ld s9, 176(a0)
-ld s10, 184(a0)
-ld s11, 192(a0)
-ld ra, 200(a0)
-ld a5, 208(a0)
-ld a4, 216(a0)
-ld a3, 224(a0)
-ld a2, 232(a0)
-ld a1, 240(a0)
-ld a6, 248(a0)
-sd a6, 248(a0)
-sd a1, 240(a0)
-sd a2, 232(a0)
-sd a3, 224(a0)
-sd a4, 216(a0)
-sd a5, 208(a0)
-sd ra, 200(a0)
-sd s11, 192(a0)
-sd s10, 184(a0)
-sd s9, 176(a0)
-sd s8, 168(a0)
-sd s7, 160(a0)
-sd s6, 152(a0)
-sd s4, 144(a0)
-sd s3, 136(a0)
-sd s2, 128(a0)
-sd s1, 120(a0)
-sd s0, 112(a0)
-sd t6, 104(a0)
-sd t5, 96(a0)
-sd t4, 88(a0)
-sd t3, 80(a0)
-sd t2, 72(a0)
-sd t1, 64(a0)
-sd t0, 56(a0)
-sd a7, 48(a0)
-ld a1, 0(sp)
-sd a1, 40(a0)
-ld a1, 8(sp)
-sd a1, 32(a0)
-ld a1, 16(sp)
-sd a1, 24(a0)
-ld a1, 24(sp)
-sd a1, 16(a0)
-ld a1, 32(sp)
-sd a1, 8(a0)
-ld a1, 40(sp)
-sd a1, 0(a0)
-lui a0, 524288
-addi a0, a0, -1
+slli s1, s1, 32
+slli a1, s3, 32
+lwu a2, 128(a0)
+lw a3, 132(a0)
+lwu a4, 136(a0)
+lw a5, 140(a0)
+lwu a6, 144(a0)
+lw s4, 148(a0)
+lwu s6, 152(a0)
+lw s7, 156(a0)
+or s3, s1, s0
+or s2, a1, s2
+slli a3, a3, 32
+slli a5, a5, 32
+or s1, a3, a2
+or s0, a5, a4
+slli s4, s4, 32
+slli s7, s7, 32
+lwu a1, 160(a0)
+lw a2, 164(a0)
+lwu a3, 168(a0)
+lw a4, 172(a0)
+lwu t1, 176(a0)
+lw s9, 180(a0)
+lwu s10, 184(a0)
+lw s11, 188(a0)
+or s8, s4, a6
+or s7, s7, s6
+slli a2, a2, 32
+slli a4, a4, 32
+or s6, a2, a1
+or s4, a4, a3
+slli s9, s9, 32
+slli s11, s11, 32
+lwu a6, 192(a0)
+lw a2, 196(a0)
+lwu a3, 200(a0)
+lw a4, 204(a0)
+lwu t2, 208(a0)
+lw a5, 212(a0)
+lwu t3, 216(a0)
+lw a1, 220(a0)
+or t4, s9, t1
+or ra, s11, s10
+slli a2, a2, 32
+slli a4, a4, 32
+or s11, a2, a6
+or s10, a4, a3
+slli t0, a5, 32
+slli a7, a1, 32
+lwu t1, 224(a0)
+lw a6, 228(a0)
+lwu s9, 232(a0)
+lw a4, 236(a0)
+lwu a5, 240(a0)
+lw a3, 244(a0)
+lwu a2, 248(a0)
+lw a1, 252(a0)
+or t2, t0, t2
+or t0, a7, t3
+slli a6, a6, 32
+slli a4, a4, 32
+or a7, a6, t1
+or a6, a4, s9
+slli a3, a3, 32
+slli a4, a1, 32
+or a1, a3, a5
+or s9, a4, a2
+ld a2, 80(sp)
+sw a2, 0(a0)
+srli a2, a2, 32
+sw a2, 4(a0)
+ld a3, 88(sp)
+srli a2, a3, 32
+sw a3, 8(a0)
+sw a2, 12(a0)
+ld a2, 48(sp)
+sw a2, 16(a0)
+srli a2, a2, 32
+sw a2, 20(a0)
+ld a3, 56(sp)
+srli a2, a3, 32
+sw a3, 24(a0)
+sw a2, 28(a0)
+ld a2, 64(sp)
+sw a2, 32(a0)
+srli a2, a2, 32
+sw a2, 36(a0)
+ld a3, 72(sp)
+srli a2, a3, 32
+sw a3, 40(a0)
+sw a2, 44(a0)
+ld a2, 16(sp)
+sw a2, 48(a0)
+srli a2, a2, 32
+sw a2, 52(a0)
+ld a3, 24(sp)
+srli a2, a3, 32
+sw a3, 56(a0)
+sw a2, 60(a0)
+ld a2, 32(sp)
+sw a2, 64(a0)
+srli a2, a2, 32
+sw a2, 68(a0)
+ld a3, 40(sp)
+srli a2, a3, 32
+sw a3, 72(a0)
+sw a2, 76(a0)
+sw t6, 80(a0)
+srli a2, t6, 32
+sw a2, 84(a0)
+srli a2, t5, 32
+sw t5, 88(a0)
+sw a2, 92(a0)
+ld a2, 0(sp)
+sw a2, 96(a0)
+srli a2, a2, 32
+sw a2, 100(a0)
+ld a3, 8(sp)
+srli a2, a3, 32
+sw a3, 104(a0)
+sw a2, 108(a0)
+sw s3, 112(a0)
+srli a2, s3, 32
+sw a2, 116(a0)
+srli a2, s2, 32
+sw s2, 120(a0)
+sw a2, 124(a0)
+sw s1, 128(a0)
+srli s1, s1, 32
+sw s1, 132(a0)
+srli a2, s0, 32
+sw s0, 136(a0)
+sw a2, 140(a0)
+sw s8, 144(a0)
+srli a2, s8, 32
+sw a2, 148(a0)
+srli a2, s7, 32
+sw s7, 152(a0)
+sw a2, 156(a0)
+sw s6, 160(a0)
+srli a2, s6, 32
+sw a2, 164(a0)
+srli a2, s4, 32
+sw s4, 168(a0)
+sw a2, 172(a0)
+sw t4, 176(a0)
+srli a2, t4, 32
+sw a2, 180(a0)
+srli a2, ra, 32
+sw ra, 184(a0)
+sw a2, 188(a0)
+sw s11, 192(a0)
+srli a2, s11, 32
+sw a2, 196(a0)
+srli a2, s10, 32
+sw s10, 200(a0)
+sw a2, 204(a0)
+srli a2, t2, 32
+sw t2, 208(a0)
+sw a2, 212(a0)
+srli a2, t0, 32
+sw t0, 216(a0)
+sw a2, 220(a0)
+srli a2, a7, 32
+sw a7, 224(a0)
+sw a2, 228(a0)
+srli a2, a6, 32
+sw a6, 232(a0)
+sw a2, 236(a0)
+srli a2, a1, 32
+sw a1, 240(a0)
 lui a1, %hi(G.2)
-sw a0, 0(a0)
-sd a6, %lo(G.2)(a1)
-li a0, -1
+sw a2, 244(a0)
+srli a2, s9, 32
+sw s9, 248(a0)
+sw a2, 252(a0)
+addi a0, a1, %lo(G.2)
+sw s9, 0(a0)
+li a1, -1
+sw a2, 4(a0)
+srli a0, a1, 32
+sw a1, 0(a0)
+srli a1, a1, 1
+sw a0, 4(a0)
+srli a0, a1, 32
+sw a1, 8(a0)
 lui a1, %hi(G)
-sw a0, 0(a0)
+sw a0, 12(a0)
 sh zero, %lo(G)(a1)
-ld ra, 136(sp)
-ld s0, 128(sp)
-ld s1, 120(sp)
-ld s2, 112(sp)
-ld s3, 104(sp)
-ld s4, 96(sp)
-ld s6, 88(sp)
-ld s7, 80(sp)
-ld s8, 72(sp)
-ld s9, 64(sp)
-ld s10, 56(sp)
-ld s11, 48(sp)
-addi sp, sp, 144
+ld ra, 184(sp)
+ld s0, 176(sp)
+ld s1, 168(sp)
+ld s2, 160(sp)
+ld s3, 152(sp)
+ld s4, 144(sp)
+ld s6, 136(sp)
+ld s7, 128(sp)
+ld s8, 120(sp)
+ld s9, 112(sp)
+ld s10, 104(sp)
+ld s11, 96(sp)
+addi sp, sp, 192
 ret

Occurrences (1):

Generated 2026-10-15 08:05 UTC.