regression: +104 insts: rotl_32_mask_or_64_or_32 (rotl-rotr.ll)

Snippet:

@G.1 = external global i32

; Function Attrs: nounwind
define i32 @rotl_32_mask_or_64_or_32(i32 %x, i32 %y) #0 {
  %A10 = alloca i1, align 1
  store i1 true, ptr %A10, align 1
  %A8 = alloca i1, align 1
  store i1 false, ptr %A8, align 1
  %A = alloca i128, align 8
  store i128 18446744073709551616, ptr %A, align 4
  %L = load i128, ptr %A, align 4
  switch i128 %L, label %SW_D [
    i128 10313260519407683672, label %SW_C
    i128 10113334039659144235, label %SW_C1
    i128 1018002067521868096, label %SW_C2
    i128 14037542181371330795, label %SW_C3
    i128 5836119722115023178, label %SW_C4
    i128 13476525337644816333, label %SW_C5
    i128 8589347238422132671, label %SW_C6
    i128 14943832940757854221, label %SW_C7
  ]

BB:                                               ; preds = %SW_C7, %SW_C5, %SW_C4, %SW_C2, %SW_C1, %SW_C
  %a = or i32 %y, 64
  %b = shl i32 %x, %a
  %c = sub i32 0, %y
  %d = or i32 %c, 32
  %e = lshr i32 %x, %d
  %f = or i32 %b, %e
  ret i32 %f

SW_D:                                             ; preds = %0
  %LGV = load i32, ptr @G.1, align 4
  ret i32 %LGV

SW_C:                                             ; preds = %0
  br label %BB

SW_C1:                                            ; preds = %0
  br label %BB

SW_C2:                                            ; preds = %0
  br label %BB

SW_C3:                                            ; preds = %0
  ret i32 %x

SW_C4:                                            ; preds = %SW_C4, %0
  %L9 = load i1, ptr %A8, align 1
  br i1 %L9, label %BB, label %SW_C4

SW_C5:                                            ; preds = %SW_C5, %0
  %L11 = load i1, ptr %A10, align 1
  br i1 %L11, label %SW_C5, label %BB

SW_C6:                                            ; preds = %0
  ret i32 %x

SW_C7:                                            ; preds = %0
  br label %BB
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,45 +1,167 @@
 addi sp, sp, -32
-li a1, 1
+addi a2, sp, 8
+li a5, 1
+sw zero, 4(a2)
+sw a5, 8(a2)
+sw zero, 12(a2)
+sw zero, 8(sp)
+lw a2, 12(sp)
+lw a3, 8(sp)
+lw a4, 16(sp)
+lui a6, 586241
+sb a5, 31(sp)
+lui a5, 947633
+addi a6, a6, -52
+addi a7, a5, -1960
 sb zero, 30(sp)
-sb a1, 31(sp)
-sw zero, 8(sp)
-sw zero, 12(sp)
-sw a1, 16(sp)
-sw zero, 20(sp)
-seqz a2, a1
-addi a2, a2, -1
-and a2, a2, a1
-j .L0
-bnez a2, .L1
-lui a0, 652828
-addi a0, a0, -1156
-or a0, a1, a0
-beqz a0, .L2
-j .L3
-lbu a0, 30(sp)
+beq a2, a6, .L0
+sltu a5, a2, a6
+j .L1
+.L0:
+sltu a5, a3, a7
+.L1:
+xori t2, a5, 1
+lw a5, 20(sp)
+sltiu t1, a4, 0
+beqz a4, .L2
+xori t2, t1, 1
+slti t0, a5, 0
+bnez a5, .L3
 .L4:
-beqz a0, .L4
-j .L2
-.L0:
-bnez a2, .L5
-lui a0, 980913
-addi a0, a0, -36
-or a0, a1, a0
-beqz a0, .L2
-j .L3
-lbu a0, 31(sp)
+bnez t2, .L5
 .L6:
-bnez a0, .L6
-j .L2
-.L1:
+lui a6, 488248
+lui a7, 92707
+addi a6, a6, -562
+addi a7, a7, 1983
+beq a2, a6, .L7
+sltu t2, a2, a6
+xori t2, t2, 1
+bnez a4, .L8
+j .L9
+.L2:
+slti t0, a5, 0
+beqz a5, .L4
 .L3:
+xori t2, t0, 1
+beqz t2, .L6
+.L5:
+lui t2, 797942
+lui t3, 426804
+addi t2, t2, -451
+addi t3, t3, 235
+beq a2, t2, .L10
+sltu t4, a2, t2
+xori t4, t4, 1
+bnez a4, .L11
+j .L12
+.L7:
+sltu t2, a3, a7
+xori t2, t2, 1
+beqz a4, .L9
+.L8:
+xori t2, t1, 1
+.L9:
+beqz a5, .L13
+xori t2, t0, 1
+beqz t2, .L14
+.L15:
+xor a7, a3, a7
+xor a6, a2, a6
+or a6, a7, a6
+or a4, a4, a5
+or a5, a6, a4
+beqz a5, .L16
+lui a5, 986110
+lui a6, 574876
+addi a5, a5, 1067
+addi a6, a6, 1977
+j .L17
+.L13:
+bnez t2, .L15
+.L14:
+lui a6, 652305
+lui a7, 57867
+addi a6, a6, 320
+addi a7, a7, -1156
+xor a6, a3, a6
+xor a7, a2, a7
+or a6, a6, a7
+or a4, a4, a5
+or a5, a6, a4
+beqz a5, .L18
+lui a5, 357652
+lui a6, 331745
+addi a5, a5, 330
+addi a6, a6, -9
+xor a3, a3, a5
+xor a2, a2, a6
+or a2, a3, a2
+or a2, a2, a4
+bnez a2, .L19
+lbu a2, 30(sp)
+andi a2, a2, 1
+.L20:
+beqz a2, .L20
+j .L18
+.L10:
+sltu t4, a3, t3
+xori t4, t4, 1
+beqz a4, .L12
+.L11:
+xori t4, t1, 1
+.L12:
+beqz a5, .L21
+xori t4, t0, 1
+or a4, a4, a5
+beqz t4, .L22
+.L23:
+xor a5, a3, t3
+xor a6, a2, t2
+or a5, a5, a6
+or a5, a5, a4
+beqz a5, .L16
+lui a5, 264819
+lui a6, 849459
+addi a5, a5, -2035
+addi a6, a6, -1822
+.L17:
+xor a3, a3, a5
+xor a2, a2, a6
+or a2, a3, a2
+or a2, a2, a4
+beqz a2, .L18
+j .L19
+.L21:
+or a4, a4, a5
+bnez t4, .L23
+.L22:
+xor a5, a3, a7
+xor a6, a2, a6
+or a5, a5, a6
+or a5, a5, a4
+beqz a5, .L18
+lui a5, 609773
+lui a6, 766052
+addi a5, a5, 1997
+addi a6, a6, -924
+xor a3, a3, a5
+xor a2, a2, a6
+or a2, a3, a2
+or a2, a2, a4
+bnez a2, .L19
+lbu a2, 31(sp)
+andi a2, a2, 1
+.L24:
+bnez a2, .L24
+.L18:
+ori a1, a1, 64
+sll a0, a0, a1
+.L16:
+addi sp, sp, 32
+ret
+.L19:
 lui a0, %hi(G.1)
 lw a0, %lo(G.1)(a0)
 addi sp, sp, 32
 ret
-.L5:
-j .L3
-.L2:
-li a0, 0
-addi sp, sp, 32
-ret

Occurrences (1):

Generated 2026-10-15 08:05 UTC.