regression: +103 insts: test_i8_z_store (short-forward-branch-opt-qcloads.ll)

Run:explore-bc8218b282-20261015-075519
Kind:regression
Category:+103 insts: test_i8_z_store (short-forward-branch-opt-qcloads.ll)
Occurrences:1 in 1 configs, 1 test files
Snippet from:short-forward-branch-opt-qcloads.1ec622275d.ll (mutant of short-forward-branch-opt-qcloads.ll) @test_i8_z_store via llvm-extract
Config:-verify-machineinstrs -mtriple=riscv32 -mattr=+xqcilo
Local check:reproduces at bc8218b282
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

@G.1 = external global i32
@G.2 = external global i1

; Function Attrs: nounwind
define i32 @test_i8_z_store(ptr %base, i1 zeroext %x, i32 %b, ptr %base1, i32 %c) #0 {
entry:
  %A = alloca i128, align 8
  store i128 18446744073709551616, ptr %A, align 4
  %L = load i128, ptr %A, align 4
  switch i128 %L, label %SW_D [
    i128 10313260519407683672, label %SW_C
    i128 10113334039659144235, label %SW_C1
    i128 1018002067521868096, label %SW_C2
    i128 14037542181371330795, label %SW_C3
    i128 5836119722115023178, label %SW_C4
    i128 13476525337644816333, label %SW_C5
    i128 8589347238422132671, label %SW_C6
    i128 14943832940757854221, label %SW_C7
  ]

BB:                                               ; preds = %SW_C7, %SW_C6, %SW_C5, %SW_C4, %SW_C2, %SW_C1, %SW_C
  %addr = getelementptr i8, ptr %base, i32 10000
  %val = load i8, ptr %addr, align 1
  %ext = zext i8 %val to i32
  store i32 %c, ptr %base1, align 4
  %res = select i1 %x, i32 %ext, i32 %b
  ret i32 %res

SW_D:                                             ; preds = %entry
  %LGV = load i32, ptr @G.1, align 4
  ret i32 %LGV

SW_C:                                             ; preds = %entry
  br label %BB

SW_C1:                                            ; preds = %entry
  br label %BB

SW_C2:                                            ; preds = %entry
  br label %BB

SW_C3:                                            ; preds = %entry
  ret i32 %b

SW_C4:                                            ; preds = %SW_C4, %entry
  br i1 %x, label %BB, label %SW_C4

SW_C5:                                            ; preds = %entry
  br label %BB

SW_C6:                                            ; preds = %entry
  br label %BB

SW_C7:                                            ; preds = %SW_C7, %entry
  %LGV8 = load i1, ptr @G.2, align 1
  br i1 %LGV8, label %SW_C7, label %BB
}

attributes #0 = { nounwind }

Reproduce:

llc -verify-machineinstrs -mtriple=riscv32 -mattr=+xqcilo -global-isel snippet.ll -o -
llc -verify-machineinstrs -mtriple=riscv32 -mattr=+xqcilo -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,49 +1,170 @@
-addi sp, sp, -16
+addi sp, sp, -32
+sw s0, 28(sp)
 li a5, 1
-sw zero, 0(sp)
-sw zero, 4(sp)
-sw a5, 8(sp)
-sw zero, 12(sp)
-seqz a6, a5
-addi a6, a6, -1
-and a6, a6, a5
-j .L0
-bnez a6, .L1
-lui a6, 652828
-addi a6, a6, -1156
-or a5, a5, a6
-beqz a5, .L2
-j .L3
+addi t0, sp, 8
+sw zero, 8(sp)
+sw zero, 4(t0)
+sw a5, 8(t0)
+lw a5, 12(sp)
+lw a6, 8(sp)
+lw a7, 16(sp)
+lui t1, 586241
+lui t2, 947633
+addi t1, t1, -52
+sw zero, 12(t0)
+addi t2, t2, -1960
+beq a5, t1, .L0
+sltu t0, a5, t1
+j .L1
+.L0:
+sltu t0, a6, t2
+.L1:
+xori t5, t0, 1
+lw t0, 20(sp)
+sltiu t4, a7, 0
+bnez a7, .L2
+slti t3, t0, 0
+bnez t0, .L3
 .L4:
-beqz a1, .L4
-j .L2
-.L0:
-bnez a6, .L5
-lui a6, 980913
-addi a6, a6, -36
-or a5, a5, a6
-beqz a5, .L2
-.L1:
-j .L3
+bnez t5, .L5
+.L6:
+lui t1, 488248
+lui t2, 92707
+addi t1, t1, -562
+addi t2, t2, 1983
+beq a5, t1, .L7
+sltu t5, a5, t1
+xori t5, t5, 1
+bnez a7, .L8
+j .L9
+.L2:
+xori t5, t4, 1
+slti t3, t0, 0
+beqz t0, .L4
+.L3:
+xori t5, t3, 1
+beqz t5, .L6
 .L5:
-j .L3
+lui t5, 797942
+lui t6, 426804
+addi t5, t5, -451
+addi t6, t6, 235
+beq a5, t5, .L10
+sltu s0, a5, t5
+xori s0, s0, 1
+bnez a7, .L11
+j .L12
+.L7:
+sltu t5, a6, t2
+xori t5, t5, 1
+beqz a7, .L9
+.L8:
+xori t5, t4, 1
+.L9:
+bnez t0, .L13
+bnez t5, .L14
+.L15:
+lui t1, 652305
+lui t2, 57867
+addi t1, t1, 320
+addi t2, t2, -1156
+xor t1, a6, t1
+xor t2, a5, t2
+or t1, t1, t2
+or a7, a7, t0
+or t0, t1, a7
+beqz t0, .L16
+lui t0, 357652
+lui t1, 331745
+addi t0, t0, 330
+addi t1, t1, -9
+xor a6, a6, t0
+xor a5, a5, t1
+or a5, a6, a5
+or a5, a5, a7
+bnez a5, .L17
+.L18:
+beqz a1, .L18
+j .L16
+.L10:
+sltu s0, a6, t6
+xori s0, s0, 1
+beqz a7, .L12
+.L11:
+xori s0, t4, 1
+.L12:
+bnez t0, .L19
+or a7, a7, t0
+bnez s0, .L20
+.L21:
+xor t0, a6, t2
+xor t1, a5, t1
+or t0, t0, t1
+or t0, t0, a7
+beqz t0, .L16
+lui t0, 609773
+lui t1, 766052
+addi t0, t0, 1997
+addi t1, t1, -924
+j .L22
+.L13:
+xori t5, t3, 1
+beqz t5, .L15
+.L14:
+xor t2, a6, t2
+xor t1, a5, t1
+or t1, t2, t1
+or a7, a7, t0
+or t0, t1, a7
+beqz t0, .L16
+lui t0, 986110
+lui t1, 574876
+addi t0, t0, 1067
+addi t1, t1, 1977
+.L22:
+xor a6, a6, t0
+xor a5, a5, t1
+or a5, a6, a5
+or a5, a5, a7
+beqz a5, .L16
+j .L17
+.L19:
+xori s0, t3, 1
+or a7, a7, t0
+beqz s0, .L21
+.L20:
+xor t0, a6, t6
+xor t1, a5, t5
+or t0, t0, t1
+or t0, t0, a7
+beqz t0, .L23
+lui t0, 264819
+lui t1, 849459
+addi t0, t0, -2035
+addi t1, t1, -1822
+xor a6, a6, t0
+xor a5, a5, t1
+or a5, a6, a5
+or a5, a5, a7
+bnez a5, .L17
 lui a5, %hi(G.2)
 lbu a5, %lo(G.2)(a5)
-.L6:
-bnez a5, .L6
-.L2:
-qc.e.lbu a0, 10000(a0)
+andi a5, a5, 1
+.L24:
+bnez a5, .L24
+.L16:
+lui a5, 2
+add a0, a0, a5
+lbu a0, 1808(a0)
 sw a4, 0(a3)
-bnez a1, .L7
+bnez a1, .L25
+.L23:
 mv a0, a2
-.L7:
-addi sp, sp, 16
+.L25:
+lw s0, 28(sp)
+addi sp, sp, 32
 ret
-.L3:
+.L17:
 lui a0, %hi(G.1)
 lw a0, %lo(G.1)(a0)
-addi sp, sp, 16
-ret
-mv a0, a2
-addi sp, sp, 16
-ret
+j .L25

Occurrences (1):

InputFunctionConfig
short-forward-branch-opt-qcloads.1ec622275d.ll (mutant of short-forward-branch-opt-qcloads.ll)test_i8_z_store-verify-machineinstrs -mtriple=riscv32 -mattr=+xqcilo

Generated 2026-10-15 08:05 UTC.