regression: +106 insts: muloti_test (umulo-128-legalisation-lowering.ll)

Snippet:

@G = external global i128
@G.1 = external global i16
@G.3 = external global { i128, i1 }

; Function Attrs: nounwind memory(none)
define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
start:
  %B = add i128 170141183460469231731687303715884105727, %r
  %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
  %1 = extractvalue { i128, i1 } %0, 0
  %I = insertvalue { i128, i1 } %0, i128 %r, 0
  %2 = extractvalue { i128, i1 } %0, 1
  %3 = zext i1 %2 to i8
  %4 = insertvalue { i128, i8 } poison, i128 %1, 0
  %5 = insertvalue { i128, i8 } %4, i8 %3, 1
  %B1 = and i16 42, 0
  store i128 %B, ptr @G, align 4
  store i16 %B1, ptr @G.1, align 2
  store { i128, i1 } %I, ptr @G.3, align 4
  ret { i128, i8 } %5
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1

attributes #0 = { nounwind memory(none) }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -mattr=+m -global-isel snippet.ll -o -
llc -mtriple=riscv32 -mattr=+m -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,141 +1,246 @@
-addi sp, sp, -48
-sw s0, 44(sp)
-sw s1, 40(sp)
-sw s2, 36(sp)
-sw s3, 32(sp)
-sw s4, 28(sp)
-sw s5, 24(sp)
-sw s6, 20(sp)
-sw s7, 16(sp)
-sw s8, 12(sp)
-sw s9, 8(sp)
-sw s10, 4(sp)
-lw a3, 8(a2)
-lw a6, 0(a1)
-lw t2, 4(a1)
-lw a5, 0(a2)
+addi sp, sp, -80
+sw ra, 76(sp)
+sw s0, 72(sp)
+sw s1, 68(sp)
+sw s2, 64(sp)
+sw s3, 60(sp)
+sw s4, 56(sp)
+sw s5, 52(sp)
+sw s6, 48(sp)
+sw s7, 44(sp)
+sw s8, 40(sp)
+sw s9, 36(sp)
+sw s10, 32(sp)
+sw s11, 28(sp)
+sw a0, 24(sp)
+lui t3, 524288
+lw a6, 0(a2)
 lw a4, 4(a2)
+lw a5, 8(a2)
+lw t0, 12(a2)
+addi a0, a6, -1
+addi t4, a4, -1
+sltiu t5, a0, -1
+lw t2, 0(a1)
+lw s6, 4(a1)
 lw a7, 8(a1)
-lw t0, 12(a1)
-lw a1, 12(a2)
-snez a2, a3
-mulhu t3, a6, a5
-mul t4, t2, a5
-or t1, a5, a4
-mul t5, a6, a4
-snez t1, t1
-addi t6, a3, -1
-mulhu s0, t2, a5
-mulhu s1, a6, a4
+lw t1, 12(a1)
+add a0, t4, t5
+sw a0, 16(sp)
+addi t3, t3, -1
+seqz a1, a0
+sltu t4, t4, a4
+and a1, a1, t5
+addi t5, a5, -1
+or a1, t4, a1
+mulhu t6, t2, a6
+mul s0, t2, a4
+add a0, t5, a1
+sw a0, 12(sp)
+mul s1, s6, a6
+sltu t5, t5, a5
+seqz s2, a0
+mulhu s3, s6, a6
+mulhu s4, t2, a4
+and a1, s2, a1
+mul s2, t2, a5
+or a1, t5, a1
+mul t5, s6, a4
+add t3, t0, t3
+add s5, t6, s0
+add a1, t3, a1
+sw a1, 8(sp)
+add a0, s5, s1
+sw a0, 20(sp)
+sltu t3, s5, s0
+sltu s0, a0, s1
+mul s1, a7, a6
+add s3, s3, s4
+sltu s4, s3, s4
+add s3, s3, s2
+sltu s2, s3, s2
+add s3, s3, t5
+add s2, s4, s2
+sltu t5, s3, t5
+add s0, t3, s0
+add s2, s2, t5
+mulhu s5, a7, a6
+mulhu s7, s6, a4
+add t3, s3, s1
+mulhu t5, t2, a5
+sltu s3, t3, s1
+mul s1, t2, t0
+add s3, s2, s3
+add t6, t3, s0
+sltu s0, t6, s0
+mul s2, s6, a5
+add s0, s3, s0
+mul s4, a7, a4
+mul s3, t1, a6
+add s5, s5, s7
+sltu s7, s5, s7
+add s8, s5, t5
+sltu s9, s8, t5
+add s8, s8, s1
+add s7, s7, s9
+sltu s9, s8, s1
+add s7, s7, s9
+add s8, s8, s2
+sltu s9, s8, s2
+add s8, s8, s4
+add s7, s7, s9
+sltu s9, s8, s4
+mulhu s10, t1, a6
+mulhu s11, a7, a4
+add s9, s7, s9
+mulhu ra, s6, a5
+add s8, s8, s3
+mulhu s7, t2, t0
+sltu a0, s8, s3
+add s8, s8, s0
+add a0, s9, a0
+sltu s9, s8, s0
+add s9, a0, s9
+mul a0, s6, t0
+mul s8, a7, a5
+add s10, s10, s11
+sltu s11, s10, s11
+add s10, s10, ra
+sltu ra, s10, ra
+add s10, s10, s7
+add s11, s11, ra
+sltu s7, s10, s7
+mul ra, t1, a4
+add s7, s11, s7
+sltiu s11, s10, 0
+add s10, s10, a0
+add s7, s7, s11
+sltu a2, s10, a0
+mulhu a1, t1, a4
+add a0, s7, a2
+add s10, s10, s8
+sltu s7, s10, s8
+mulhu s8, a7, a5
+add s10, s10, ra
+mulhu a2, s6, t0
+add s7, a0, s7
+sltu ra, s10, ra
+sltiu a0, s10, 0
+add a0, ra, a0
+mv ra, a1
+add t3, s7, a0
+sltu a1, a1, a1
+add ra, ra, s8
+mul s7, a7, t0
+sltu s8, ra, s8
+add ra, ra, a2
+add a1, a1, s8
+sltu a2, ra, a2
+mv ra, ra
+mul s8, t1, a5
+add a1, a1, a2
+sltu a2, ra, zero
+add a1, a1, a2
+sltiu a2, ra, 0
+add a2, a2, a2
+add ra, ra, s7
+add a1, a1, a2
+sltu a2, ra, s7
 add a2, a1, a2
-add t1, t6, t1
-sltu t6, t1, t6
-lui s2, 524288
-addi s2, s2, -1
-add t3, t4, t3
-add s3, a2, s2
-add a2, t5, t3
-sltu t3, t3, t4
-sltu t4, a2, t5
-add t3, s0, t3
-add s1, s1, t4
-mul t5, t2, a4
-mul s0, a3, a6
-mul s6, a7, a5
-mulhu s5, t2, a4
-mul s7, t2, a3
-mul s8, a1, a6
-mul s9, a4, a7
-mul s10, t0, a5
-mulhu s4, a3, a6
-mulhu s2, a7, a5
-add t4, s3, t6
-add s1, t3, s1
-sltu t3, s1, t3
-add s1, t5, s1
-add s0, s6, s0
-add t6, s5, t3
-add t3, s1, s0
-sltu t5, s1, t5
-add s5, s8, s7
-add s3, s10, s9
-add s5, s4, s5
-add s3, s2, s3
-add s7, s3, s5
-sltu s0, s0, s6
-add s6, t6, t5
-add s0, s7, s0
-sltu s1, t3, s1
-add t5, s6, s0
-seqz t6, a5
+add t4, s10, s9
+sltu s7, t4, s9
+add s9, ra, s8
+sltu s8, s9, s8
+sltiu a0, s9, 0
+mulhu a1, t1, a5
+add s8, s8, a0
+mulhu s10, a7, t0
+add t3, t3, s7
+add s8, a2, s8
+add s9, s9, t3
+add a0, s8, a0
+sltu s6, s9, t3
+add s6, a0, s6
+mv t3, a1
+sltu a1, a1, a1
+add t3, t3, s10
+mv a0, a1
+sltu a1, t3, s10
+add a0, a0, a1
+mv t3, t3
+lui a1, %hi(G)
+sltu s7, t3, zero
+add a0, a0, s7
+addi a1, a1, %lo(G)
+addi s7, a6, -1
+sw s7, 0(a1)
+mul s7, t1, t0
+lw s8, 16(sp)
+sw s8, 4(a1)
+mv t3, t3
+lw s8, 12(sp)
+sw s8, 8(a1)
+sltu s8, t3, zero
+lw s10, 8(sp)
+sw s10, 12(a1)
+sltiu a1, t3, 0
+mulhu t1, t1, t0
+add a0, a0, s8
+add s8, a1, a1
+add t3, t3, s7
+add a0, a0, s8
+sltu s7, t3, s7
+add a1, a1, s7
+sltiu s7, t3, 0
+add a0, a0, a1
+add a1, s7, s7
+add a1, a1, s7
+mv t1, t1
+add a0, a0, a1
+mv t1, t1
+add t3, t3, s6
+sltu a1, t3, s6
+add a0, a0, a1
 add t5, t5, s1
-sub t6, a4, t6
-addi s0, a5, -1
-beq t5, s6, .L0
-sltu s1, t5, s6
-.L0:
-mulhu s6, a1, a6
-sltu s4, s5, s4
-mulhu s5, t2, a3
-snez t2, t2
-mulhu s7, t0, a5
-snez s8, a1
-mulhu s9, a4, a7
-sltu s2, s3, s2
-snez s3, a4
-and t2, s8, t2
-snez s8, t0
-and s3, s8, s3
-snez s6, s6
-or t2, t2, s6
-snez s5, s5
-or s4, s5, s4
-snez s5, s7
-or t2, t2, s4
-snez s4, s9
-or s3, s3, s5
-or s2, s4, s2
-or s4, a3, a1
-or a7, a7, t0
-snez t0, s4
-snez a7, a7
-or s2, s3, s2
-and a7, a7, t0
-or a7, a7, s2
-or t0, t2, s1
-or a7, a7, t0
-mul a6, a6, a5
-lui t0, %hi(G)
-addi t0, t0, %lo(G)
-andi a7, a7, 1
-sw s0, 0(t0)
-sw t6, 4(t0)
-sw t1, 8(t0)
-sw t4, 12(t0)
-lui t0, %hi(G.1)
-sh zero, %lo(G.1)(t0)
-lui t0, %hi(G.3)
-addi t0, t0, %lo(G.3)
-sw a5, 0(t0)
-sw a4, 4(t0)
-sw a3, 8(t0)
-sw a1, 12(t0)
-sb a7, 16(t0)
-sb a7, 16(a0)
-sw a6, 0(a0)
-sw a2, 4(a0)
-sw t3, 8(a0)
-sw t5, 12(a0)
-lw s0, 44(sp)
-lw s1, 40(sp)
-lw s2, 36(sp)
-lw s3, 32(sp)
-lw s4, 28(sp)
-lw s5, 24(sp)
-lw s6, 20(sp)
-lw s7, 16(sp)
-lw s8, 12(sp)
-lw s9, 8(sp)
-lw s10, 4(sp)
-addi sp, sp, 48
+add s2, s2, s4
+add t5, s5, t5
+add s2, s2, s3
+add a0, t1, a0
+add t5, t5, s2
+add t5, t5, s0
+or a1, t4, s9
+mul a2, t2, a6
+or a1, a1, t3
+lui a3, %hi(G.3)
+or a0, a1, a0
+lui a1, %hi(G.1)
+addi a3, a3, %lo(G.3)
+sh zero, %lo(G.1)(a1)
+sw a6, 0(a3)
+sw a4, 4(a3)
+sw a5, 8(a3)
+sw t0, 12(a3)
+snez a0, a0
+sb a0, 16(a3)
+lw a1, 24(sp)
+sw a2, 0(a1)
+lw a2, 20(sp)
+sw a2, 4(a1)
+sw t6, 8(a1)
+sw t5, 12(a1)
+sb a0, 16(a1)
+lw ra, 76(sp)
+lw s0, 72(sp)
+lw s1, 68(sp)
+lw s2, 64(sp)
+lw s3, 60(sp)
+lw s4, 56(sp)
+lw s5, 52(sp)
+lw s6, 48(sp)
+lw s7, 44(sp)
+lw s8, 40(sp)
+lw s9, 36(sp)
+lw s10, 32(sp)
+lw s11, 28(sp)
+addi sp, sp, 80
 ret

Occurrences (1):

Generated 2026-10-15 08:05 UTC.