crash: Assertion failed: (DstTy.isVector() && SrcVecTy.isVector() && "Extract subvector VTs must be vectors!"), function buildInstr, file MachineIRBuilder.cpp

Run:main-04ca53e65f-20261014-105623
Kind:crash
Category:Assertion failed: (DstTy.isVector() && SrcVecTy.isVector() && "Extract subvector VTs must be vectors!"), function buildInstr, file MachineIRBuilder.cpp
Occurrences:16 in 4 configs, 3 test files
Snippet from:inline-asm-fixed-v-constraint.ll @constraint_vr_fixed via llvm-extract + llvm-reduce
Config:-mtriple=riscv32 -mattr=+v -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:https://godbolt.org/z/h179b39Yn (llc-assertions-trunk, checked 2026-10-14 11:03 UTC): G reproduces

Snippet:

define <1 x i8> @constraint_vr_fixed(<1 x i8> %0) {
  ret <1 x i8> %0
}

Compiler Explorer panes:

PaneOptionsExitInstsstderr
GlobalISel-mtriple=riscv32 -mattr=+v -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.*1340llc: /root/llvm-project/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:1512: virtual llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr(unsigned int, llvm::ArrayRef<llvm::DstOp>, llvm::ArrayRef<llvm::SrcOp>, std::optional<unsigned int>): Assertion `DstTy.isVector() && SrcVecTy.isVector() && "Extract subvector VTs must be vectors!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
SelectionDAG (control)-mtriple=riscv32 -mattr=+v -verify-machineinstrs -global-isel=001-

Reproduce:

llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

llc: /home/runner/work/llvm-fuzz/llvm-fuzz/llvm-project/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:1513: virtual MachineInstrBuilder llvm::MachineIRBuilder::buildInstr(unsigned int, ArrayRef<DstOp>, ArrayRef<SrcOp>, std::optional<unsigned int>): Assertion `DstTy.isVector() && SrcVecTy.isVector() && "Extract subvector VTs must be vectors!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0.	Program arguments: /home/runner/work/llvm-fuzz/llvm-fuzz/llvm-project/build/bin/llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* -o -
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'IRTranslator' on function '@constraint_vr_fixed'
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  llc       0x000055fc5ce2d79b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 43
1  llc       0x000055fc5ce2a641 llvm::sys::RunSignalHandlers() + 369
2  llc       0x000055fc5ce2e21b
3  libc.so.6 0x00007f185e245330
4  libc.so.6 0x00007f185e29ec0c pthread_kill + 284
5  libc.so.6 0x00007f185e24527e gsignal + 30
6  libc.so.6 0x00007f185e2288ff abort + 223
7  libc.so.6 0x00007f185e22881b
8  libc.so.6 0x00007f185e23b517
9  llc       0x000055fc5ef8c012 llvm::MachineIRBuilder::buildInstr(unsigned int, llvm::ArrayRef<llvm::DstOp>, llvm::ArrayRef<llvm::SrcOp>, std::optional<unsigned int>) + 11506
10 llc       0x000055fc5eea30ef llvm::CSEMIRBuilder::buildInstr(unsigned int, llvm::ArrayRef<llvm::DstOp>, llvm::ArrayRef<llvm::SrcOp>, std::optional<unsigned int>) + 2991
11 llc       0x000055fc5ef87d7c llvm::MachineIRBuilder::buildExtractSubvector(llvm::DstOp const&, llvm::SrcOp const&, unsigned int) + 76
12 llc       0x000055fc5e04a54f
13 llc       0x000055fc5ee98ee0 llvm::CallLowering::handleAssignments(llvm::CallLowering::ValueHandler&, llvm::SmallVectorImpl<llvm::CallLowering::ArgInfo>&, llvm::CCState&, llvm::SmallVectorImpl<llvm::CCValAssign>&, llvm::MachineIRBuilder&, llvm::ArrayRef<llvm::Register>) const + 928
14 llc       0x000055fc5e0476ec
15 llc       0x000055fc5ef05260 llvm::IRTranslatorImpl::runOnMachineFunction(llvm::MachineFunction&, llvm::function_ref<llvm::GISelCSEInfo* ()>, bool, llvm::function_ref<llvm::AAResults* ()>, llvm::function_ref<llvm::BranchProbabilityInfo* ()>, llvm::function_ref<llvm::AssumptionCache* ()>, llvm::TargetLibraryInfo*, llvm::LibcallLoweringInfo const*, llvm::SSPLayoutInfo*) + 3552
16 llc       0x000055fc5ef0650d llvm::IRTranslatorLegacy::runOnMachineFunction(llvm::MachineFunction&) + 733
17 llc       0x000055fc5d3f4d2d llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 653
18 llc       0x000055fc5d184cd7 llvm::FPPassManager::runOnFunction(llvm::Function&) + 871
19 llc       0x000055fc5d18d1d2 llvm::FPPassManager::runOnModule(llvm::Module&) + 50
20 llc       0x000055fc5d185a80 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 2000
21 llc       0x000055fc5ce34df8 llcMain + 12056
22 llc       0x000055fc5cd7062f main + 63
23 libc.so.6 0x00007f185e22a1ca
24 libc.so.6 0x00007f185e22a28b __libc_start_main + 139
25 llc       0x000055fc5cd70525 _start + 37

Occurrences (16):

InputFunctionConfig
inline-asm-fixed-v-constraint.ll-mtriple=riscv32 -mattr=+v -verify-machineinstrs
inline-asm-fixed-v-constraint.ll-mtriple=riscv64 -mattr=+v -verify-machineinstrs
smulh.ll-mtriple=riscv32 -mattr=+m,+v
smulh.ll-mtriple=riscv64 -mattr=+m,+v
umulh.ll-mtriple=riscv32 -mattr=+m,+v
umulh.ll-mtriple=riscv64 -mattr=+m,+v
inline-asm-fixed-v-constraint.35309ac3aa.ll (mutant of inline-asm-fixed-v-constraint.ll)-mtriple=riscv32 -mattr=+v -verify-machineinstrs
inline-asm-fixed-v-constraint.3c0a1b68a2.ll (mutant of inline-asm-fixed-v-constraint.ll)-mtriple=riscv32 -mattr=+v -verify-machineinstrs
inline-asm-fixed-v-constraint.3df7ea9e3d.ll (mutant of inline-asm-fixed-v-constraint.ll)-mtriple=riscv32 -mattr=+v -verify-machineinstrs
inline-asm-fixed-v-constraint.7a5ba08d90.ll (mutant of inline-asm-fixed-v-constraint.ll)-mtriple=riscv64 -mattr=+v -verify-machineinstrs
inline-asm-fixed-v-constraint.b32e701d3e.ll (mutant of inline-asm-fixed-v-constraint.ll)-mtriple=riscv64 -mattr=+v -verify-machineinstrs
inline-asm-fixed-v-constraint.db44c1c75d.ll (mutant of inline-asm-fixed-v-constraint.ll)-mtriple=riscv64 -mattr=+v -verify-machineinstrs
smulh.182838ff33.ll (mutant of smulh.ll)-mtriple=riscv32 -mattr=+m,+v
smulh.86f675d719.ll (mutant of smulh.ll)-mtriple=riscv64 -mattr=+m,+v
umulh.95054b2aaa.ll (mutant of umulh.ll)-mtriple=riscv32 -mattr=+m,+v
umulh.de687d47f5.ll (mutant of umulh.ll)-mtriple=riscv64 -mattr=+m,+v

Generated 2026-10-15 08:05 UTC.