fallback: legalize: G_FNEG s16

Run:main-04ca53e65f-20261014-105623
Kind:fallback
Category:legalize: G_FNEG s16
Occurrences:99 in 15 configs, 2 test files
Snippet from:half-bitmanip-dagcombines.ll @fneg via llvm-extract
Config:-mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define half @fneg(half %a) #0 {
  %1 = fneg half %a
  ret half %1
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(s16) = G_FNEG %0:_ (in function: fneg)
warning: Instruction selection used fallback path for fneg

Occurrences (99) (first 50):

InputFunctionConfig
half-arith.llfneg_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfsgnjn_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfnmadd_h_3-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfnmadd_nsz-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.llfneg_h-mtriple=riscv32 -verify-machineinstrs
half-arith.llfsgnjn_h-mtriple=riscv32 -verify-machineinstrs
half-arith.llfnmadd_h_3-mtriple=riscv32 -verify-machineinstrs
half-arith.llfnmadd_nsz-mtriple=riscv32 -verify-machineinstrs
half-arith.llfneg_h-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfsgnjn_h-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfnmadd_h_3-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfnmadd_nsz-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.llfneg_h-mtriple=riscv64 -verify-machineinstrs
half-arith.llfsgnjn_h-mtriple=riscv64 -verify-machineinstrs
half-arith.llfnmadd_h_3-mtriple=riscv64 -verify-machineinstrs
half-arith.llfnmadd_nsz-mtriple=riscv64 -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv32 -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv32 -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv64 -target-abi lp64 -mattr=+zfhmin -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv64 -target-abi lp64 -mattr=+zfhmin -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv64 -target-abi lp64 -mattr=+zhinx -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv64 -target-abi lp64 -mattr=+zhinx -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv64 -target-abi lp64 -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv64 -target-abi lp64 -verify-machineinstrs
half-bitmanip-dagcombines.llfneg-mtriple=riscv64 -verify-machineinstrs
half-bitmanip-dagcombines.llfcopysign_fneg-mtriple=riscv64 -verify-machineinstrs
half-arith.04ef595b6f.ll (mutant of half-arith.ll)fnmadd_h_3-mtriple=riscv32 -verify-machineinstrs
half-arith.109afb59d3.ll (mutant of half-arith.ll)fnmadd_h_3-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi ilp32
half-arith.200a3f0607.ll (mutant of half-arith.ll)fnmadd_nsz-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi ilp32
half-arith.240625360b.ll (mutant of half-arith.ll)fnmadd_h_3-mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64
half-arith.26ce342410.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv32 -verify-machineinstrs
half-arith.37f3a7d312.ll (mutant of half-arith.ll)fnmadd_nsz-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32
half-arith.3e8aa9e07c.ll (mutant of half-arith.ll)fnmadd_h_3-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.4acd81f656.ll (mutant of half-arith.ll)fnmadd_nsz-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f
half-arith.60cc614512.ll (mutant of half-arith.ll)fnmadd_nsz-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.62f96e6f57.ll (mutant of half-arith.ll)fnmadd_h_3-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.6bfd989946.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv64 -verify-machineinstrs
half-arith.6d6389fb52.ll (mutant of half-arith.ll)fnmadd_h_3-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64
half-arith.844b32f4e4.ll (mutant of half-arith.ll)fnmadd_nsz-mtriple=riscv32 -verify-machineinstrs
half-arith.a34ecf14d6.ll (mutant of half-arith.ll)fsgnjn_h-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f
half-arith.a84312824e.ll (mutant of half-arith.ll)fnmadd_nsz-mtriple=riscv64 -verify-machineinstrs
half-arith.be6f29a4fc.ll (mutant of half-arith.ll)fnmadd_nsz-mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64

Generated 2026-10-15 08:05 UTC.