fallback: legalize: G_FPTOSI

fallback: legalize: G_FPTOSI_SAT s64

Run:	main-04ca53e65f-20261014-105623
Kind:	fallback
Category:	legalize: G_FPTOSI_SAT s64
Occurrences:	38 in 6 configs, 2 test files
Snippet from:	double-convert.ll @fcvt_l_d_sat via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i64 @fcvt_l_d_sat(double %a) #0 {
start:
  %0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
  ret i64 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.fptosi.sat.i64.f64(double) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s64) = G_FPTOSI_SAT %0:_(s64) (in function: fcvt_l_d_sat)
warning: Instruction selection used fallback path for fcvt_l_d_sat

Occurrences (38):

Input	Function	Config
double-convert.ll	fcvt_l_d_sat	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-convert.ll	fcvt_l_d_sat	`-mtriple=riscv32 -verify-machineinstrs`
double-convert.ll	fcvt_l_d_sat	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-convert.ll	fcvt_l_d_sat	`-mtriple=riscv64 -verify-machineinstrs`
double-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_round_si64	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_round_si64	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_round_si64	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_round_si64	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-convert.14e2f2e132.ll (mutant of double-convert.ll)	fcvt_l_d_sat	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-convert.2b4f3ab0ba.ll (mutant of double-convert.ll)	fcvt_l_d_sat	`-mtriple=riscv32 -verify-machineinstrs`
double-convert.4845330a4a.ll (mutant of double-convert.ll)	fcvt_l_d_sat	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-convert.4c100e2abe.ll (mutant of double-convert.ll)	fcvt_l_d_sat	`-mtriple=riscv64 -verify-machineinstrs`
double-convert.9061862cfe.ll (mutant of double-convert.ll)	fcvt_l_d_sat	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-convert.f128dd6c49.ll (mutant of double-convert.ll)	fcvt_l_d_sat	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`
double-round-conv-sat.3be064a741.ll (mutant of double-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32`
double-round-conv-sat.6874e7db68.ll (mutant of double-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64`
double-round-conv-sat.8b2e0125d1.ll (mutant of double-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv32 -mattr=+d -verify-machineinstrs -target-abi=ilp32d`
double-round-conv-sat.bbe2941b3b.ll (mutant of double-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d`

Generated 2026-10-15 08:05 UTC.