fallback: legalize: G_FPTOUI_SAT s32

Run:main-04ca53e65f-20261014-105623
Kind:fallback
Category:legalize: G_FPTOUI_SAT s32
Occurrences:52 in 6 configs, 2 test files
Snippet from:float-convert.ll @fcvt_wu_s_sat via llvm-extract
Config:-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i32 @fcvt_wu_s_sat(float %a) #0 {
start:
  %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
  ret i32 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.fptoui.sat.i32.f32(float) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s32) = G_FPTOUI_SAT %0:_(s32) (in function: fcvt_wu_s_sat)
warning: Instruction selection used fallback path for fcvt_wu_s_sat

Occurrences (52) (first 50):

InputFunctionConfig
float-convert.llfcvt_wu_s_sat-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.llfcvt_wu_s_sat-mtriple=riscv32 -verify-machineinstrs
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv32 -verify-machineinstrs
float-convert.llfcvt_wu_s_sat-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-convert.llfcvt_wu_s_sat-mtriple=riscv64 -verify-machineinstrs
float-convert.llfcvt_wu_s_sat_zext-mtriple=riscv64 -verify-machineinstrs
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_round_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_round_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_round_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.lltest_floor_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_ceil_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_trunc_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_round_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_roundeven_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.lltest_rint_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-convert.6c036a5bc8.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv32 -verify-machineinstrs
float-convert.847d5c830e.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv64 -verify-machineinstrs
float-convert.c3d36f3741.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-convert.dfc0422379.ll (mutant of float-convert.ll)fcvt_wu_s_sat_zext-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.0aee1e5f9f.ll (mutant of float-round-conv-sat.ll)test_floor_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.0aee1e5f9f.ll (mutant of float-round-conv-sat.ll)test_round_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.23bbda5300.ll (mutant of float-round-conv-sat.ll)test_floor_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.23bbda5300.ll (mutant of float-round-conv-sat.ll)test_round_ui32-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64
float-round-conv-sat.39ddfd032a.ll (mutant of float-round-conv-sat.ll)test_floor_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.39ddfd032a.ll (mutant of float-round-conv-sat.ll)test_round_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.63f2997124.ll (mutant of float-round-conv-sat.ll)test_floor_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.63f2997124.ll (mutant of float-round-conv-sat.ll)test_round_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.7c139bdf3a.ll (mutant of float-round-conv-sat.ll)test_floor_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.7c139bdf3a.ll (mutant of float-round-conv-sat.ll)test_round_ui32-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f
float-round-conv-sat.7ce1101de1.ll (mutant of float-round-conv-sat.ll)test_floor_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.7ce1101de1.ll (mutant of float-round-conv-sat.ll)test_round_ui32-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f
float-round-conv-sat.c007e521ab.ll (mutant of float-round-conv-sat.ll)test_floor_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32
float-round-conv-sat.c007e521ab.ll (mutant of float-round-conv-sat.ll)test_round_ui32-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32

Generated 2026-10-15 08:05 UTC.