fallback: legalize: G_FPTOUI

fallback: legalize: G_FPTOUI_SAT s64,s16

Run:	main-04ca53e65f-20261014-105623
Kind:	fallback
Category:	legalize: G_FPTOUI_SAT s64,s16
Occurrences:	86 in 22 configs, 2 test files
Snippet from:	half-convert.ll @fcvt_lu_h_sat via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i64 @fcvt_lu_h_sat(half %a) #0 {
start:
  %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)
  ret i64 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.fptoui.sat.i64.f16(half) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %2:_(s64) = G_FPTOUI_SAT %0:_(s16) (in function: fcvt_lu_h_sat)
warning: Instruction selection used fallback path for fcvt_lu_h_sat

Occurrences (86) (first 50):

Input	Function	Config
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv32 -mattr=+d -target-abi=ilp32d -verify-machineinstrs`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs -target-abi ilp32d`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi ilp32d`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi ilp32f`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32f`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv32 -verify-machineinstrs`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv64 -mattr=+d -target-abi=lp64d -verify-machineinstrs`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs -target-abi lp64d`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs -target-abi lp64d`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi lp64f`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi lp64f`
half-convert.ll	fcvt_lu_h_sat	`-mtriple=riscv64 -verify-machineinstrs`
half-round-conv-sat.ll	test_floor_ui64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_ceil_ui64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_trunc_ui64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_roundeven_ui64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_rint_ui64	`-mtriple=riscv32 -mattr=+zfh -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_floor_ui64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_ceil_ui64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_trunc_ui64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_roundeven_ui64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_rint_ui64	`-mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs -target-abi=ilp32f`
half-round-conv-sat.ll	test_floor_ui64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_ceil_ui64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_trunc_ui64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_roundeven_ui64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_rint_ui64	`-mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_floor_ui64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_ceil_ui64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_trunc_ui64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_round_ui64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_roundeven_ui64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_rint_ui64	`-mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi=ilp32`
half-round-conv-sat.ll	test_floor_ui64	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_ceil_ui64	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_trunc_ui64	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_round_ui64	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_roundeven_ui64	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_rint_ui64	`-mtriple=riscv64 -mattr=+zfh -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_floor_ui64	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_ceil_ui64	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_trunc_ui64	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_round_ui64	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_roundeven_ui64	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi=lp64f`
half-round-conv-sat.ll	test_rint_ui64	`-mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs -target-abi=lp64f`

Generated 2026-10-15 08:05 UTC.