fallback: legalize: G_INTRINSIC s32,<2 x s16>

Run:	main-04ca53e65f-20261014-105623
Kind:	fallback
Category:	legalize: G_INTRINSIC s32,<2 x s16>
Occurrences:	54 in 2 configs, 2 test files
Snippet from:	rvp-simd-32.ll @test_predsum_i16x2_i32 via llvm-extract
Config:	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

define i32 @test_predsum_i16x2_i32(<2 x i16> %a, i32 %b) {
  %res = call i32 @llvm.riscv.predsum.i32.v2i16(<2 x i16> %a, i32 %b)
  ret i32 %res
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.riscv.predsum.i32.v2i16(<2 x i16>, i32) #0

attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %5:_(s32) = G_INTRINSIC intrinsic(@llvm.riscv.predsum), %0:_(<2 x s16>), %1:_(s32) (in function: test_predsum_i16x2_i32)
warning: Instruction selection used fallback path for test_predsum_i16x2_i32

Occurrences (54) (first 50):

Input	Function	Config
rvp-mul-parts-acc-fold.ll	macc_h00	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	macc_h01	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	macc_h11	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	maccu_h00	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	maccu_h01	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	maccu_h11	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	maccsu_h00	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	maccsu_h11	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	multi_use	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	swapped_operands	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.ll	accumulate_chain	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_predsum_i16x2_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_predsumu_u16x2_u32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mqacc_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mqacc_h01_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mqacc_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mqracc_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mqracc_h01_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mqracc_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mul_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mul_h01_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mul_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulu_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulu_h01_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulu_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulsu_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulsu_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2add_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2add_x_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2addu_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pmq2add_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pmqr2add_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2sadd_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2sadd_x_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2sub_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2sub_x_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_pm2addsu_v2i16_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_macc_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_macc_h01_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_macc_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_maccu_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_maccu_h01_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_maccu_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_maccsu_h00_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_maccsu_h11_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulh_h0_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulh_h1_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulhsu_h0_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-simd-32.ll	test_mulhsu_h1_i32	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`
rvp-mul-parts-acc-fold.82f0f6af2e.ll (mutant of rvp-mul-parts-acc-fold.ll)	maccu_h11	`-mtriple=riscv64 -mattr=+experimental-p,+m,+zbb -verify-machineinstrs`

Generated 2026-10-15 08:05 UTC.