fallback: legalize: G_INTRINSIC_W_SIDE_EFFECTS <2 x s32>,p0,s64,<2 x s1>,s32

Run:main-04ca53e65f-20261014-105623
Kind:fallback
Category:legalize: G_INTRINSIC_W_SIDE_EFFECTS <2 x s32>,p0,s64,<2 x s1>,s32
Occurrences:5 in 1 configs, 1 test files
Snippet from:di-assignment-tracking-vector.ll @foo via llvm-extract
Config:-mtriple=riscv64 -enable-misched=false
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

define void @foo() #0 !dbg !4 {
entry:
  %i = alloca i64, align 8, !DIAssignID !11
  %j = alloca i64, align 8, !DIAssignID !12
  %sar_height.i = getelementptr i8, ptr %i, i64 24
  store ptr %sar_height.i, ptr null, align 8
  %vui.i = getelementptr i8, ptr %i, i64 44
  %0 = load i32, ptr %vui.i, align 4
  %sar_width.i = getelementptr i8, ptr %i, i64 20
  %i_sar_width.i = getelementptr i8, ptr %i, i64 48
  %j_sar_width.j = getelementptr i8, ptr %j, i64 48
    #dbg_assign(i32 1010, !8, !DIExpression(), !11, ptr %i_sar_width.i, !DIExpression(), !13)
    #dbg_assign(i32 2121, !10, !DIExpression(), !12, ptr %i_sar_width.i, !DIExpression(), !13)
  %1 = load <2 x i32>, ptr %sar_width.i, align 4
  call void @llvm.experimental.vp.strided.store.v2i32.p0.i64(<2 x i32> %1, ptr align 4 %i_sar_width.i, i64 -4, <2 x i1> splat (i1 true), i32 2)
  call void @llvm.experimental.vp.strided.store.v2i32.p0.i64(<2 x i32> %1, ptr align 4 %j_sar_width.j, i64 -4, <2 x i1> splat (i1 true), i32 2), !DIAssignID !14
    #dbg_assign(i32 1010, !8, !DIExpression(), !15, ptr %i_sar_width.i, !DIExpression(), !13)
    #dbg_assign(i32 2121, !10, !DIExpression(), !14, ptr %i_sar_width.i, !DIExpression(), !13)
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
declare void @llvm.experimental.vp.strided.store.v2i32.p0.i64(<2 x i32>, ptr captures(none), i64, <2 x i1>, i32) #1

attributes #0 = { "target-features"="+v" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3}

!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang version 21.0.0git", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
!1 = !DIFile(filename: "test.c", directory: "/")
!2 = !{i32 2, !"Debug Info Version", i32 3}
!3 = !{i32 7, !"debug-info-assignment-tracking", i1 true}
!4 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: !1, file: !1, line: 1, type: !5, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !7)
!5 = !DISubroutineType(types: !6)
!6 = !{}
!7 = !{!8, !10}
!8 = !DILocalVariable(name: "i", scope: !4, file: !1, line: 7, type: !9)
!9 = !DIBasicType(name: "int32_t", size: 32, encoding: DW_ATE_signed)
!10 = !DILocalVariable(name: "j", scope: !4, file: !1, line: 7, type: !9)
!11 = distinct !DIAssignID()
!12 = distinct !DIAssignID()
!13 = !DILocation(line: 5, scope: !4)
!14 = distinct !DIAssignID()
!15 = distinct !DIAssignID()

Reproduce:

llc -mtriple=riscv64 -enable-misched=false -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -enable-misched=false -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.experimental.vp.strided.store), %13:_(<2 x s32>), %12:_(p0), %14:_(s64), %15:_(<2 x s1>), %17:_(s32) (in function: foo)
warning: Instruction selection used fallback path for foo

Occurrences (5):

InputFunctionConfig
di-assignment-tracking-vector.llfoo-mtriple=riscv64 -enable-misched=false
di-assignment-tracking-vector.4e4d4892df.ll (mutant of di-assignment-tracking-vector.ll)foo-mtriple=riscv64 -enable-misched=false
di-assignment-tracking-vector.d6493866f7.ll (mutant of di-assignment-tracking-vector.ll)foo-mtriple=riscv64 -enable-misched=false
di-assignment-tracking-vector.e6d3ebe6e3.ll (mutant of di-assignment-tracking-vector.ll)foo-mtriple=riscv64 -enable-misched=false
di-assignment-tracking-vector.feb8e722e2.ll (mutant of di-assignment-tracking-vector.ll)foo-mtriple=riscv64 -enable-misched=false

Generated 2026-10-15 08:05 UTC.