fallback: unable to lower arguments

Run:main-04ca53e65f-20261014-105623
Kind:fallback
Category:unable to lower arguments
Occurrences:1087 in 24 configs, 20 test files
Snippet from:bfloat-convert-half.ll @test_h_bf16 via llvm-extract
Config:-mtriple=riscv32 -mattr=+zfhmin,+zfbfmin -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define half @test_h_bf16(bfloat %a) #0 {
  %r = bitcast bfloat %a to half
  ret half %r
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -mattr=+zfhmin,+zfbfmin -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+zfhmin,+zfbfmin -verify-machineinstrs -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to lower arguments: half (bfloat) (in function: test_h_bf16)
warning: Instruction selection used fallback path for test_h_bf16

Occurrences (1087) (first 50):

InputFunctionConfig
bfloat-arith.llfadd_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfsub_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfmul_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfdiv_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfsqrt_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfsgnj_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfneg_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfsgnjn_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfabs_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfmin_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfmax_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfmadd_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfmsub_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmadd_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmadd_s_2-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmadd_s_3-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmadd_nsz-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmsub_bf16-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmsub_bf16_2-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfmadd_bf16_contract-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfmsub_bf16_contract-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmadd_bf16_contract-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfnmsub_bf16_contract-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-arith.llfadd_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfsub_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfmul_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfdiv_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfsqrt_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfsgnj_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfneg_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfsgnjn_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfabs_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfmin_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfmax_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfmadd_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfmsub_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmadd_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmadd_s_2-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmadd_s_3-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmadd_nsz-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmsub_bf16-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmsub_bf16_2-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfmadd_bf16_contract-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfmsub_bf16_contract-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmadd_bf16_contract-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-arith.llfnmsub_bf16_contract-mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs -target-abi lp64f
bfloat-br-fcmp.llbr_fcmp_false-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-br-fcmp.llbr_fcmp_oeq-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-br-fcmp.llbr_fcmp_oeq_alt-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f
bfloat-br-fcmp.llbr_fcmp_ogt-mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs -target-abi ilp32f

Generated 2026-10-15 08:05 UTC.