regression: +72 insts: ashr_16bytes_wordOff (wide-scalar-shift-by-byte-multiple-legalization.ll)

Run:main-04ca53e65f-20261014-105623
Kind:regression
Category:+72 insts: ashr_16bytes_wordOff (wide-scalar-shift-by-byte-multiple-legalization.ll)
Occurrences:1 in 1 configs, 1 test files
Snippet from:wide-scalar-shift-by-byte-multiple-legalization.ca43c377d3.ll (mutant of wide-scalar-shift-by-byte-multiple-legalization.ll) @ashr_16bytes_wordOff via llvm-extract
Config:-mtriple=riscv32 -verify-machineinstrs
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

@G = external global half
@G.1 = external global half

; Function Attrs: nounwind
define void @ashr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) #0 {
  %LGV1 = load half, ptr @G.1, align 2
  %LGV = load half, ptr @G, align 2
  %src = load i128, ptr %src.ptr, align 1
  %wordOff = load i128, ptr %wordOff.ptr, align 1
  %C = fcmp uge half %LGV, %LGV1
  %bitOff = shl i128 %wordOff, 5
  %res = ashr i128 %src, %bitOff
  store i128 %res, ptr %dst, align 1
  store i1 %C, ptr poison, align 1
  ret void
}

attributes #0 = { nounwind }

Reproduce:

llc -mtriple=riscv32 -verify-machineinstrs -global-isel snippet.ll -o -
llc -mtriple=riscv32 -verify-machineinstrs -global-isel=0 snippet.ll -o -

Assembly diff (SelectionDAG vs GlobalISel):

--- sdag
+++ gisel
@@ -1,123 +1,215 @@
-addi sp, sp, -80
-sw ra, 76(sp)
-sw s0, 72(sp)
-sw s1, 68(sp)
-sw s2, 64(sp)
-sw s3, 60(sp)
-sw s4, 56(sp)
-sw s5, 52(sp)
-sw s6, 48(sp)
-sw s7, 44(sp)
-sw s8, 40(sp)
+addi sp, sp, -64
+sw ra, 60(sp)
+sw s0, 56(sp)
+sw s1, 52(sp)
+sw s2, 48(sp)
+sw s3, 44(sp)
+sw s4, 40(sp)
+sw s5, 36(sp)
+sw s6, 32(sp)
+sw s7, 28(sp)
+sw s8, 24(sp)
+sw s9, 20(sp)
+sw s10, 16(sp)
+sw s11, 12(sp)
 mv s0, a2
-lui a2, %hi(G.1)
-lbu a3, 1(a0)
-lbu a4, 2(a0)
-lbu a5, 3(a0)
-lbu a6, 0(a0)
-slli a3, a3, 8
+lbu s5, 0(a0)
+lbu a2, 1(a0)
+lbu a3, 2(a0)
+lbu a4, 3(a0)
+lbu s6, 4(a0)
+lbu a5, 7(a0)
+lbu s9, 5(a0)
+lbu a6, 6(a0)
+lbu a7, 9(a0)
+lbu t0, 11(a0)
+lbu t1, 8(a0)
+lbu t2, 10(a0)
+slli a4, a4, 8
+slli a5, a5, 8
+or s8, a4, a3
+or s7, a5, a6
+slli a7, a7, 8
+slli t0, t0, 8
+or a3, t0, t2
+lbu a4, 13(a0)
+or a5, a7, t1
+slli a3, a3, 16
+lbu a6, 12(a0)
+lbu a7, 14(a0)
+lbu a0, 15(a0)
+lbu t0, 1(a1)
+slli a4, a4, 8
+lbu t1, 0(a1)
+lbu t2, 2(a1)
+lbu a1, 3(a1)
+or s3, a3, a5
+or a3, a4, a6
+slli a0, a0, 8
+slli t0, t0, 8
+or a4, a0, a7
+or a5, t0, t1
+lui a0, %hi(G.1)
+slli a1, a1, 8
+or a1, a1, t2
+lui a6, %hi(G)
+lh s1, %lo(G.1)(a0)
+lh a0, %lo(G)(a6)
+slli s10, a2, 8
+slli s9, s9, 8
 slli a4, a4, 16
-slli a5, a5, 24
-lbu a7, 4(a0)
-lbu t0, 5(a0)
-or a3, a3, a6
-or a4, a5, a4
-or s3, a4, a3
-lbu a3, 6(a0)
-lbu a4, 7(a0)
-slli t0, t0, 8
-lbu a5, 9(a0)
-or a6, t0, a7
-lbu a7, 8(a0)
-lbu t0, 10(a0)
-lbu t1, 11(a0)
-slli a3, a3, 16
-slli a4, a4, 24
-or a3, a4, a3
-slli a5, a5, 8
-or s4, a3, a6
-or a3, a5, a7
-slli t0, t0, 16
-slli t1, t1, 24
-lbu a4, 12(a0)
-lbu a5, 13(a0)
-lbu a6, 14(a0)
-lbu a7, 15(a0)
-or t0, t1, t0
-lui t1, %hi(G)
-lhu a0, %lo(G.1)(a2)
-lhu s1, %lo(G)(t1)
-slli a5, a5, 8
-lbu s5, 0(a1)
-slli a6, a6, 16
-slli s6, a7, 24
-or a4, a5, a4
-or a1, s6, a6
-or s7, t0, a3
-or s8, a1, a4
+slli a1, a1, 16
+or s4, a4, a3
+or s11, a1, a5
 call __extendhfsf2
 mv s2, a0
 mv a0, s1
 call __extendhfsf2
-mv a1, s2
+mv a1, a0
+mv a0, s2
 call __ltsf2
-srai a1, s6, 31
-slli s5, s5, 2
-sw a1, 24(sp)
-sw a1, 28(sp)
-sw a1, 32(sp)
-sw a1, 36(sp)
-andi a1, s5, 12
-addi a2, sp, 8
-sw s3, 8(sp)
-sw s4, 12(sp)
-sw s7, 16(sp)
-sw s8, 20(sp)
-add a1, a2, a1
-lw a2, 8(a1)
-srli a0, a0, 31
+slli a4, s11, 5
+li a6, 32
+neg t2, a4
+srl t0, s3, a4
+sll t3, s4, t2
+bltu a4, a6, .L0
+sra a2, s4, a4
+j .L1
+.L0:
+or a2, t0, t3
+.L1:
+or a3, s10, s5
+slli a5, s8, 16
+or a7, s9, s6
+slli s7, s7, 16
+mv a1, s3
+beqz a4, .L2
+mv a1, a2
+.L2:
+or a5, a5, a3
+or a3, s7, a7
+bltu a4, a6, .L3
+srai a2, s4, 31
+srl t4, a3, a4
+j .L4
+.L3:
+srl a7, a5, a4
+sll t1, a3, t2
+sra a2, s4, a4
+or t4, a7, t1
+.L4:
+li a7, 64
+mv t1, a5
+beqz a4, .L5
+mv t1, t4
+.L5:
+sub t5, a7, a4
+bltu a4, a6, .L6
+li t4, 0
+bgeu t5, a6, .L7
+.L8:
+neg t6, t5
+srl t6, s3, t6
+sll t2, s3, t2
+or s1, t6, t3
+j .L9
+.L6:
+srl t4, a3, a4
+bltu t5, a6, .L8
+.L7:
+li t2, 0
+sll s1, s3, t5
+.L9:
+addi t6, a4, -64
+mv t3, s4
+beqz t5, .L10
+mv t3, s1
+.L10:
+bltu t6, a6, .L11
+sra t0, s4, t6
+bnez t6, .L12
+j .L13
+.L11:
+neg t5, t6
+sll t5, s4, t5
+or t0, t0, t5
+beqz t6, .L13
+.L12:
+mv s3, t0
+.L13:
+bltu t6, a6, .L14
+srai a6, s4, 31
+bltu a4, a7, .L15
+j .L16
+.L14:
+sra a6, s4, a4
+bgeu a4, a7, .L16
+.L15:
+or s3, t1, t2
+or a6, t4, t3
+.L16:
+slti a0, a0, 0
+bnez a4, .L17
 xori a0, a0, 1
-lw a3, 4(a1)
-lw a4, 0(a1)
-lw a1, 12(a1)
-srli a5, a2, 16
-srli a6, a2, 24
-srli a7, a2, 8
-sb a2, 8(s0)
-sb a7, 9(s0)
+bltu a4, a7, .L18
+.L19:
+srai a1, s4, 31
+mv a2, a1
+.L18:
+lui a4, 16
+srli a6, a5, 16
+addi a4, a4, -1
+srli a7, a5, 24
+and t0, a5, a4
+srli t0, t0, 8
+sb a5, 0(s0)
+sb t0, 1(s0)
+sb a6, 2(s0)
+sb a7, 3(s0)
+and a5, a3, a4
+srli a6, a3, 16
+srli a5, a5, 8
+srli a7, a3, 24
+sb a3, 4(s0)
+sb a5, 5(s0)
+sb a6, 6(s0)
+sb a7, 7(s0)
+and a3, a1, a4
+srli a5, a1, 16
+srli a3, a3, 8
+srli a6, a1, 24
+sb a1, 8(s0)
+sb a3, 9(s0)
 sb a5, 10(s0)
 sb a6, 11(s0)
-srli a2, a1, 16
-srli a5, a1, 24
-srli a6, a1, 8
-sb a1, 12(s0)
-sb a6, 13(s0)
-sb a2, 14(s0)
-sb a5, 15(s0)
-srli a1, a4, 16
-srli a2, a4, 24
-srli a5, a4, 8
-sb a4, 0(s0)
-sb a5, 1(s0)
-sb a1, 2(s0)
-sb a2, 3(s0)
-srli a1, a3, 16
-srli a2, a3, 24
-srli a4, a3, 8
-sb a3, 4(s0)
-sb a4, 5(s0)
-sb a1, 6(s0)
-sb a2, 7(s0)
+and a4, a2, a4
+srli a1, a2, 16
+srli a4, a4, 8
+srli a3, a2, 24
+sb a2, 12(s0)
+sb a4, 13(s0)
+sb a1, 14(s0)
+sb a3, 15(s0)
 sb a0, 0(a0)
-lw ra, 76(sp)
-lw s0, 72(sp)
-lw s1, 68(sp)
-lw s2, 64(sp)
-lw s3, 60(sp)
-lw s4, 56(sp)
-lw s5, 52(sp)
-lw s6, 48(sp)
-lw s7, 44(sp)
-lw s8, 40(sp)
-addi sp, sp, 80
+lw ra, 60(sp)
+lw s0, 56(sp)
+lw s1, 52(sp)
+lw s2, 48(sp)
+lw s3, 44(sp)
+lw s4, 40(sp)
+lw s5, 36(sp)
+lw s6, 32(sp)
+lw s7, 28(sp)
+lw s8, 24(sp)
+lw s9, 20(sp)
+lw s10, 16(sp)
+lw s11, 12(sp)
+addi sp, sp, 64
 ret
+.L17:
+mv a5, s3
+mv a3, a6
+xori a0, a0, 1
+bgeu a4, a7, .L19
+j .L18

Occurrences (1):

InputFunctionConfig
wide-scalar-shift-by-byte-multiple-legalization.ca43c377d3.ll (mutant of wide-scalar-shift-by-byte-multiple-legalization.ll)ashr_16bytes_wordOff-mtriple=riscv32 -verify-machineinstrs

Generated 2026-10-15 08:05 UTC.