| Run: | main-04ca53e65f-20261014-113325 |
| Kind: | crash |
| Category: | Assertion failed: (BestRC && "Couldn't find the register class"), function getCommonMinimalPhysRegClass, file TargetRegisterInfo.cpp |
| Occurrences: | 509 in 55 configs, 54 test files |
| Snippet from: | float-frem.ll @frem_f32 via llvm-extract + llvm-reduce |
| Config: | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs |
| Local check: | reproduces at 04ca53e65f |
| Compiler Explorer: | https://godbolt.org/z/osxhGv9Ec (llc-assertions-trunk, checked 2026-10-14 11:03 UTC): G reproduces |
define float @frem_f32() {
ret float 0.000000e+00
}
| Pane | Options | Exit | Insts | stderr |
|---|---|---|---|---|
| GlobalISel | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* | 134 | 0 | llc: /root/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp:216: const TargetRegisterClass* getCommonMinimalPhysRegClass(const llvm::TargetRegisterInfo*, llvm::MCRegister, llvm::MCRegister): Assertion `BestRC && "Couldn't find the register class"' failed. PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. Stack dump: |
| SelectionDAG (control) | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -global-isel=0 | 0 | 2 | - |
llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o - llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -global-isel=0 snippet.ll -o -
llc: /home/runner/work/llvm-fuzz/llvm-fuzz/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp:216: const TargetRegisterClass *getCommonMinimalPhysRegClass(const TargetRegisterInfo *, MCRegister, MCRegister): Assertion `BestRC && "Couldn't find the register class"' failed. PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. Stack dump: 0. Program arguments: /home/runner/work/llvm-fuzz/llvm-fuzz/llvm-project/build/bin/llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* -o - 1. Running pass 'Function Pass Manager' on module '<stdin>'. 2. Running pass 'Post-RA pseudo instruction expansion pass' on function '@frem_f32' Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it): 0 llc 0x0000560d9b26c79b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 43 1 llc 0x0000560d9b269641 llvm::sys::RunSignalHandlers() + 369 2 llc 0x0000560d9b26d21b 3 libc.so.6 0x00007f4822245330 4 libc.so.6 0x00007f482229ec0c pthread_kill + 284 5 libc.so.6 0x00007f482224527e gsignal + 30 6 libc.so.6 0x00007f48222288ff abort + 223 7 libc.so.6 0x00007f482222881b 8 libc.so.6 0x00007f482223b517 9 llc 0x0000560d9b340ea8 llvm::TargetRegisterInfo::getCommonMinimalPhysRegClass(llvm::MCRegister, llvm::MCRegister) const + 248 10 llc 0x0000560d9bfd5c9f 11 llc 0x0000560d9b93a617 llvm::TargetInstrInfo::lowerCopy(llvm::MachineInstr*) const + 359 12 llc 0x0000560d9bc1b998 13 llc 0x0000560d9bc1c143 14 llc 0x0000560d9b833d2d llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 653 15 llc 0x0000560d9b5c3cd7 llvm::FPPassManager::runOnFunction(llvm::Function&) + 871 16 llc 0x0000560d9b5cc1d2 llvm::FPPassManager::runOnModule(llvm::Module&) + 50 17 llc 0x0000560d9b5c4a80 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 2000 18 llc 0x0000560d9b273df8 llcMain + 12056 19 llc 0x0000560d9b1af62f main + 63 20 libc.so.6 0x00007f482222a1ca 21 libc.so.6 0x00007f482222a28b __libc_start_main + 139 22 llc 0x0000560d9b1af525 _start + 37
| Input | Function | Config |
|---|---|---|
| codemodel-lowering.ll | -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=medium -verify-machineinstrs | |
| codemodel-lowering.ll | -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs | |
| codemodel-lowering.ll | -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs -mattr=+xqcili | |
| codemodel-lowering.ll | -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=large -verify-machineinstrs | |
| codemodel-lowering.ll | -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=medium -verify-machineinstrs | |
| codemodel-lowering.ll | -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=small -verify-machineinstrs | |
| copysign-casts.ll | -mtriple=riscv32 -verify-machineinstrs -mattr=+zdinx -target-abi ilp32 | |
| copysign-casts.ll | -mtriple=riscv64 -verify-machineinstrs -mattr=+zdinx -target-abi lp64 | |
| double-convert.ll | -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 | |
| double-convert.ll | -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64 | |
| double-mem.ll | -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 | |
| double-mem.ll | -mtriple=riscv32 -mattr=+zdinx,+zilsd -verify-machineinstrs -target-abi=ilp32 | |
| fastcc-without-f-reg.ll | -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs | |
| fastcc-without-f-reg.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs | |
| fastcc-without-f-reg.ll | -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs | |
| fastcc-without-f-reg.ll | -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs | |
| fastcc-without-f-reg.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs | |
| fastcc-without-f-reg.ll | -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs | |
| float-arith.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-arith.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-bit-preserving-dagcombines.ll | -mtriple=riscv32 -mattr=+zfinx -target-abi=ilp32 -verify-machineinstrs | |
| float-bit-preserving-dagcombines.ll | -mtriple=riscv64 -mattr=+zfinx -target-abi=lp64 -verify-machineinstrs | |
| float-bitmanip-dagcombines.ll | -mtriple=riscv32 -target-abi ilp32 -mattr=+zfinx -verify-machineinstrs | |
| float-bitmanip-dagcombines.ll | -mtriple=riscv64 -target-abi lp64 -mattr=+zfinx -verify-machineinstrs | |
| float-br-fcmp.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-br-fcmp.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-convert.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-convert.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-fcmp.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-fcmp.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-frem.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs | |
| float-frem.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs | |
| float-imm.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-imm.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-intrinsics.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-intrinsics.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-isnan.ll | -mtriple=riscv32 -mattr=+zfinx -target-abi ilp32 -verify-machineinstrs | |
| float-isnan.ll | -mtriple=riscv64 -mattr=+zfinx -target-abi lp64 -verify-machineinstrs | |
| float-mem.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-mem.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-round-conv.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-round-conv.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-select-fcmp.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-select-fcmp.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| float-select-icmp.ll | -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32 | |
| float-select-icmp.ll | -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64 | |
| half-arith.ll | -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | |
| half-arith.ll | -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | |
| half-arith.ll | -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | |
| half-arith.ll | -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 |
Generated 2026-10-15 08:05 UTC.