fallback: legalize: G_FPTOSI

fallback: legalize: G_FPTOSI_SAT s64,s32

Run:	main-04ca53e65f-20261014-113325
Kind:	fallback
Category:	legalize: G_FPTOSI_SAT s64,s32
Occurrences:	38 in 6 configs, 2 test files
Snippet from:	float-convert.ll @fcvt_l_s_sat via llvm-extract
Config:	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
Local check:	reproduces at 04ca53e65f
Compiler Explorer:	not uploaded (over --godbolt-limit or disabled)

Snippet:

; Function Attrs: nounwind
define i64 @fcvt_l_s_sat(float %a) #0 {
start:
  %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
  ret i64 %0
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.fptosi.sat.i64.f32(float) #1

attributes #0 = { nounwind }
attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %1:_(s64) = G_FPTOSI_SAT %0:_(s32) (in function: fcvt_l_s_sat)
warning: Instruction selection used fallback path for fcvt_l_s_sat

Occurrences (38):

Input	Function	Config
float-convert.ll	fcvt_l_s_sat	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-convert.ll	fcvt_l_s_sat	`-mtriple=riscv32 -verify-machineinstrs`
float-convert.ll	fcvt_l_s_sat	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-convert.ll	fcvt_l_s_sat	`-mtriple=riscv64 -verify-machineinstrs`
float-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-round-conv-sat.ll	test_round_si64	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-round-conv-sat.ll	test_round_si64	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-round-conv-sat.ll	test_round_si64	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-round-conv-sat.ll	test_floor_si64	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-round-conv-sat.ll	test_ceil_si64	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-round-conv-sat.ll	test_trunc_si64	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-round-conv-sat.ll	test_round_si64	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-round-conv-sat.ll	test_roundeven_si64	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-round-conv-sat.ll	test_rint_si64	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-convert.12a62f360b.ll (mutant of float-convert.ll)	fcvt_l_s_sat	`-mtriple=riscv64 -verify-machineinstrs`
float-convert.59faf09a15.ll (mutant of float-convert.ll)	fcvt_l_s_sat	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`
float-convert.7c6e597b95.ll (mutant of float-convert.ll)	fcvt_l_s_sat	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-convert.b8844f2236.ll (mutant of float-convert.ll)	fcvt_l_s_sat	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-convert.b9b757857f.ll (mutant of float-convert.ll)	fcvt_l_s_sat	`-mtriple=riscv32 -verify-machineinstrs`
float-convert.fda689495b.ll (mutant of float-convert.ll)	fcvt_l_s_sat	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-round-conv-sat.0863764e0b.ll (mutant of float-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv64 -mattr=+f -verify-machineinstrs -target-abi=lp64f`
float-round-conv-sat.80f528b0eb.ll (mutant of float-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs -target-abi=ilp32`
float-round-conv-sat.88b056c8db.ll (mutant of float-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs -target-abi=lp64`
float-round-conv-sat.f10a58d900.ll (mutant of float-round-conv-sat.ll)	test_ceil_si64	`-mtriple=riscv32 -mattr=+f -verify-machineinstrs -target-abi=ilp32f`

Generated 2026-10-15 08:05 UTC.