fallback: legalize: G_INSERT_SUBVECTOR <vscale x 1 x s1>,<2 x s1>

Run:main-04ca53e65f-20261014-113325
Kind:fallback
Category:legalize: G_INSERT_SUBVECTOR <vscale x 1 x s1>,<2 x s1>
Occurrences:5 in 1 configs, 1 test files
Snippet from:combine-is_fpclass.ll @extract_subvec_fixed_isneg_false via llvm-extract
Config:-mtriple=riscv64 -mattr=+v,+f,+d
Local check:reproduces at 04ca53e65f
Compiler Explorer:not uploaded (over --godbolt-limit or disabled)

Snippet:

define <2 x i1> @extract_subvec_fixed_isneg_false(<4 x float> %a0) {
  %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a0)
  %sub = call <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float> %abs, i64 0)
  %res = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %sub, /* (ninf nzero nsub nnorm) */ i32 60)
  ret <2 x i1> %res
}

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #0

; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float>, i64 immarg) #1

attributes #0 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

Reproduce:

llc -mtriple=riscv64 -mattr=+v,+f,+d -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel.* snippet.ll -o -
llc -mtriple=riscv64 -mattr=+v,+f,+d -global-isel=0 snippet.ll -o -

Local llc output:

remark: <unknown>:0:0: unable to legalize instruction: %6:_(<vscale x 1 x s1>) = G_INSERT_SUBVECTOR %5:_, %4:_(<2 x s1>), 0 (in function: extract_subvec_fixed_isneg_false)
warning: Instruction selection used fallback path for extract_subvec_fixed_isneg_false

Occurrences (5):

InputFunctionConfig
combine-is_fpclass.llextract_subvec_fixed_isneg_false-mtriple=riscv64 -mattr=+v,+f,+d
combine-is_fpclass.llextract_subvec_fixed_mixed_to_pos_isneg_false-mtriple=riscv64 -mattr=+v,+f,+d
combine-is_fpclass.llextract_subvec_fixed_straddle_isneg_unknown-mtriple=riscv64 -mattr=+v,+f,+d
combine-is_fpclass.6b8ac51c90.ll (mutant of combine-is_fpclass.ll)extract_subvec_fixed_mixed_to_pos_isneg_false-mtriple=riscv64 -mattr=+v,+f,+d
combine-is_fpclass.a8ba19f70f.ll (mutant of combine-is_fpclass.ll)extract_subvec_fixed_mixed_to_pos_isneg_false-mtriple=riscv64 -mattr=+v,+f,+d

Generated 2026-10-15 08:05 UTC.